From 6c20b65849aeda664cc40ebc0f0bab2e99768423 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Thu, 29 Dec 2016 22:54:02 +0100 Subject: intel/i945 boards: Add romstage time stamps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, some Intel 945 boards miss some or all of the time stamps *1:start of rom stage*, *2:before ram initialization*, and *3:after ram initialization*, so add them. Use the same formatting as used for the board Lenovo X60, which already has code for all the time stamps. Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/17993 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/ibase/mb899/romstage.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mainboard/ibase/mb899/romstage.c') diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 2a8965ebcb..dedbd55358 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -222,6 +223,9 @@ void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + if (bist == 0) enable_lapic(); @@ -254,7 +258,9 @@ void mainboard_romstage_entry(unsigned long bist) dump_spd_registers(); #endif + timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(s3resume ? 2 : 0, NULL); + timestamp_add_now(TS_AFTER_INITRAM); /* Perform some initialization that must run before stage2 */ early_ich7_init(); -- cgit v1.2.3