From 6beaef983aee5d886f6f8571855a92d608d98a17 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 16 Jun 2019 23:29:23 +0200 Subject: sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree Set up generic decode ranges based on the devicetree settings. Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Patrick Rudolph --- src/mainboard/hp/2570p/devicetree.cb | 1 + src/mainboard/hp/2570p/romstage.c | 2 -- src/mainboard/hp/2760p/devicetree.cb | 1 + src/mainboard/hp/2760p/romstage.c | 2 -- src/mainboard/hp/8460p/devicetree.cb | 1 + src/mainboard/hp/8460p/romstage.c | 2 -- src/mainboard/hp/8470p/devicetree.cb | 1 + src/mainboard/hp/8470p/romstage.c | 2 -- src/mainboard/hp/8770w/devicetree.cb | 1 + src/mainboard/hp/8770w/romstage.c | 2 -- src/mainboard/hp/folio_9470m/devicetree.cb | 1 + src/mainboard/hp/folio_9470m/romstage.c | 2 -- src/mainboard/hp/revolve_810_g1/devicetree.cb | 1 + src/mainboard/hp/revolve_810_g1/romstage.c | 2 -- 14 files changed, 7 insertions(+), 14 deletions(-) (limited to 'src/mainboard/hp') diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb index 585d61d134..79a84b73c2 100644 --- a/src/mainboard/hp/2570p/devicetree.cb +++ b/src/mainboard/hp/2570p/devicetree.cb @@ -46,6 +46,7 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c index 21e3ceaa3d..6401909dd5 100644 --- a/src/mainboard/hp/2570p/romstage.c +++ b/src/mainboard/hp/2570p/romstage.c @@ -28,8 +28,6 @@ void pch_enable_lpc(void) */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb index 515d20f761..a301857b7a 100644 --- a/src/mainboard/hp/2760p/devicetree.cb +++ b/src/mainboard/hp/2760p/devicetree.cb @@ -55,6 +55,7 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c index 68af61ba22..ba6f9566cf 100644 --- a/src/mainboard/hp/2760p/romstage.c +++ b/src/mainboard/hp/2760p/romstage.c @@ -27,8 +27,6 @@ void pch_enable_lpc(void) */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb index 79259b4def..a06aea9669 100644 --- a/src/mainboard/hp/8460p/devicetree.cb +++ b/src/mainboard/hp/8460p/devicetree.cb @@ -54,6 +54,7 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c index a3fb5f095f..f30c3a8d27 100644 --- a/src/mainboard/hp/8460p/romstage.c +++ b/src/mainboard/hp/8460p/romstage.c @@ -34,8 +34,6 @@ void pch_enable_lpc(void) CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/8470p/devicetree.cb b/src/mainboard/hp/8470p/devicetree.cb index 2a115cc62a..471537218e 100644 --- a/src/mainboard/hp/8470p/devicetree.cb +++ b/src/mainboard/hp/8470p/devicetree.cb @@ -55,6 +55,7 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c index a8761739d5..b1375e815b 100644 --- a/src/mainboard/hp/8470p/romstage.c +++ b/src/mainboard/hp/8470p/romstage.c @@ -33,8 +33,6 @@ void pch_enable_lpc(void) CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb index 7d74c940de..d98402c540 100644 --- a/src/mainboard/hp/8770w/devicetree.cb +++ b/src/mainboard/hp/8770w/devicetree.cb @@ -43,6 +43,7 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c index a7f6b22aa3..8956b08b7b 100644 --- a/src/mainboard/hp/8770w/romstage.c +++ b/src/mainboard/hp/8770w/romstage.c @@ -34,8 +34,6 @@ void pch_enable_lpc(void) CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb index 5d4e5b8ea2..d626934343 100644 --- a/src/mainboard/hp/folio_9470m/devicetree.cb +++ b/src/mainboard/hp/folio_9470m/devicetree.cb @@ -46,6 +46,7 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c index db3296c457..8ff7813cd9 100644 --- a/src/mainboard/hp/folio_9470m/romstage.c +++ b/src/mainboard/hp/folio_9470m/romstage.c @@ -30,8 +30,6 @@ void pch_enable_lpc(void) pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb index 4d0d6395eb..ad69ca27e4 100644 --- a/src/mainboard/hp/revolve_810_g1/devicetree.cb +++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb @@ -46,6 +46,7 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c index f62024c3e6..5f8df63f5c 100644 --- a/src/mainboard/hp/revolve_810_g1/romstage.c +++ b/src/mainboard/hp/revolve_810_g1/romstage.c @@ -33,8 +33,6 @@ void pch_enable_lpc(void) pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) -- cgit v1.2.3