From cf38facbd2255562cfbf2a2bc528794fafa5891a Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Sat, 19 Apr 2014 16:22:53 -0500 Subject: hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18 The PCIE PME pin from the APU is connected to GEVENT8, but the northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map accordingly. Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0 Signed-off-by: Alexandru Gagniuc Reviewed-on: http://review.coreboot.org/5556 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c') diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 8b48476037..df0f8fd63b 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -386,6 +386,7 @@ GPIO_CONTROL pavilion_m6_1035dx_gpio[] = { SCI_MAP_CONTROL m6_1035dx_sci_map[] = { {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE}, {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE}, + {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE}, {SCI_MAP_OHCI_12_0, PME_GPE}, {SCI_MAP_OHCI_13_0, PME_GPE}, {SCI_MAP_XHCI_10_0, PME_GPE}, -- cgit v1.2.3