From f27cb243c2f7d11a46d38da9b960c3d8a5b05676 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Sat, 4 Mar 2017 07:51:21 +0200
Subject: hp/abm: Switch away from AGESA_LEGACY
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Change-Id: Ie2f1eb5a101b9c392a7bd5cb2338dd6a6fdcfe52
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
---
 src/mainboard/hp/abm/romstage.c | 95 +++++++++--------------------------------
 1 file changed, 19 insertions(+), 76 deletions(-)

(limited to 'src/mainboard/hp/abm/romstage.c')

diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 79a8fa5692..88ba01a29c 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -14,46 +14,35 @@
  * GNU General Public License for more details.
  */
 
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/acpi.h>
 #include <arch/io.h>
-#include <arch/stages.h>
 #include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
-#include <cpu/amd/agesa/s3_resume.h>
-#include <cbmem.h>
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct5104d/nct5104d.h>
 
 #define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4)
 
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
 {
-	u32 val, t32;
 	u32 *addr32;
+	u32 t32;
 
-
-	/* Must come first to enable PCI MMCONF. */
-	amd_initmmio();
-
-	/* Set LPC decode enables. */
+	/* For serial port option, plug-in card on LPC. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev, 0x44, 0xff03ffd5);
 
 	hudson_lpc_port80();
 
+	/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+	 *  LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
+	 *  even though the register is not documented in the Kabini BKDG.
+	 *  Otherwise the serial output is bad code.
+	 */
+	outb(0xD2, 0xcd6);
+	outb(0x00, 0xcd7);
+
+
 	/* Enable the AcpiMmio space */
 	outb(0x24, 0xcd6);
 	outb(0x01, 0xcd7);
@@ -72,58 +61,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	t32 &= 0xffffff7b; // clear 2, 7
 	*addr32 = t32;
 
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x30);
-		post_code(0x31);
-
-		nct5104d_enable_uartd(SERIAL_DEV);
-		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-		console_init();
-	}
-
-	/* Halt if there was a built in self test failure */
-	post_code(0x34);
-	report_bist_failure(bist);
-
-	/* Load MPB */
-	val = cpuid_eax(1);
-	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
-	post_code(0x37);
-	agesawrapper_amdinitreset();
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
-
-	post_code(0x39);
-
-	agesawrapper_amdinitearly();
-	int s3resume = acpi_is_wakeup_s3();
-	if (!s3resume) {
-		post_code(0x40);
-		agesawrapper_amdinitpost();
-		post_code(0x41);
-		agesawrapper_amdinitenv();
-		/* TODO: Disable cache is not ok. */
-		disable_cache_as_ram();
-	} else { /* S3 detect */
-		printk(BIOS_INFO, "S3 detected\n");
-
-		post_code(0x60);
-		agesawrapper_amdinitresume();
-
-		amd_initcpuio();
-		agesawrapper_amds3laterestore();
-
-		post_code(0x61);
-		prepare_for_resume();
-	}
+	nct5104d_enable_uartd(SERIAL_DEV);
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
 
+#if 0
+	/* Was before copy_and_run. */
 	outb(0xEA, 0xCD6);
 	outb(0x1, 0xcd7);
-
-	post_code(0x50);
-	copy_and_run();
-
-	post_code(0x54);  /* Should never see this post code. */
-}
+#endif
-- 
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