From f86c3265e8014b085de08094d7a30847fa49c165 Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Fri, 10 Apr 2020 15:25:01 +0800 Subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management LTE module is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:146768983 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Pan Sheng-Liang Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40303 Tested-by: build bot (Jenkins) Reviewed-by: Marco Chen Reviewed-by: Henry Sun Reviewed-by: Justin TerAvest --- .../google/octopus/variants/bobba/overridetree.cb | 1 + .../google/octopus/variants/bobba/variant.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 6cd4c61796..c786a5d2b6 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -214,4 +214,5 @@ chip soc/intel/apollolake # Disable compliance mode register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c index 57b706795d..089337ab4c 100644 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -8,6 +8,7 @@ #include #include #include +#include enum { SKU_37_DROID = 37, /* LTE */ @@ -74,3 +75,24 @@ void variant_smi_sleep(u8 slp_typ) return; } } + + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + + if (cfg != NULL && cfg->disable_xhci_lfps_pm) { + switch (google_chromeec_get_board_sku()) { + case 37: + case 38: + case 39: + case 40: + cfg->disable_xhci_lfps_pm = 1; + return; + default: + return; + } + } +} -- cgit v1.2.3