From f04e83abbf98d1d55ec2c4fea3fb74bf2f459139 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 3 Jan 2022 19:00:00 +0000 Subject: soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` config List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 1b59ef056c..1349f69dab 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -203,9 +203,6 @@ chip soc/intel/jasperlake # - PM_CFG.SLP_LAN_MIN_ASST_WDTH register "PchPmPwrCycDur" = "1" # 1s - # Enable HECI - register "HeciEnabled" = "1" - # Set xHCI LFPS period sampling off time, the default is 9ms. register "xhci_lfps_sampling_offtime_ms" = "9" -- cgit v1.2.3