From ee28c86ccde1427e5f9aa4a110ee7d7f2629bc3c Mon Sep 17 00:00:00 2001 From: huang lin Date: Mon, 26 Jan 2015 21:04:55 +0800 Subject: rk3288: detect sdram size at runtime we use Kconfig define sdram size before, but there may use different sdram size in the same overlay, so we must detect sdram size at runtime now. If we use 4G byte sdram, we can use[0x00000000:0xff000000], since the [0xff000000:0xffffffff] is the register space. BUG=chrome-os-partner:35521 TEST=Boot from mighty BRANCH=None Change-Id: I7a167c268483743c3eaed8b71c7ec545a688270c Signed-off-by: Patrick Georgi Original-Commit-Id: ad4f27dd08c467888eee87e3d9c4ab3077751898 Original-Change-Id: Ib32aed50c9cae6db495ff3bab28266de91f3e73b Original-Signed-off-by: huang lin Original-Reviewed-on: https://chromium-review.googlesource.com/243139 Original-Reviewed-by: Julius Werner Reviewed-on: http://review.coreboot.org/9734 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/veyron_brain/Kconfig | 4 ---- src/mainboard/google/veyron_brain/romstage.c | 2 +- src/mainboard/google/veyron_danger/Kconfig | 4 ---- src/mainboard/google/veyron_danger/romstage.c | 2 +- src/mainboard/google/veyron_jerry/Kconfig | 4 ---- src/mainboard/google/veyron_jerry/romstage.c | 2 +- src/mainboard/google/veyron_mighty/Kconfig | 4 ---- src/mainboard/google/veyron_mighty/romstage.c | 2 +- src/mainboard/google/veyron_pinky/Kconfig | 4 ---- src/mainboard/google/veyron_pinky/romstage.c | 2 +- src/mainboard/google/veyron_rialto/Kconfig | 4 ---- src/mainboard/google/veyron_rialto/romstage.c | 2 +- src/mainboard/google/veyron_speedy/Kconfig | 4 ---- src/mainboard/google/veyron_speedy/romstage.c | 2 +- 14 files changed, 7 insertions(+), 35 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig index 3539d1ee2b..f8902c9bd4 100644 --- a/src/mainboard/google/veyron_brain/Kconfig +++ b/src/mainboard/google/veyron_brain/Kconfig @@ -56,10 +56,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 2048 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c index 3f9e7aaa4a..37efcaac6b 100644 --- a/src/mainboard/google/veyron_brain/romstage.c +++ b/src/mainboard/google/veyron_brain/romstage.c @@ -103,7 +103,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig index 719064ef8e..294fd97023 100644 --- a/src/mainboard/google/veyron_danger/Kconfig +++ b/src/mainboard/google/veyron_danger/Kconfig @@ -57,10 +57,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 2048 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c index c18471abe5..f3883bd28f 100644 --- a/src/mainboard/google/veyron_danger/romstage.c +++ b/src/mainboard/google/veyron_danger/romstage.c @@ -113,7 +113,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); diff --git a/src/mainboard/google/veyron_jerry/Kconfig b/src/mainboard/google/veyron_jerry/Kconfig index b9205ecaa7..7730aba89a 100644 --- a/src/mainboard/google/veyron_jerry/Kconfig +++ b/src/mainboard/google/veyron_jerry/Kconfig @@ -68,10 +68,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 2048 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index 1eed268fa7..9d19586cd5 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -112,7 +112,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); diff --git a/src/mainboard/google/veyron_mighty/Kconfig b/src/mainboard/google/veyron_mighty/Kconfig index 9bc571322c..5482e0f8e2 100644 --- a/src/mainboard/google/veyron_mighty/Kconfig +++ b/src/mainboard/google/veyron_mighty/Kconfig @@ -68,10 +68,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 2048 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c index 1eed268fa7..9d19586cd5 100644 --- a/src/mainboard/google/veyron_mighty/romstage.c +++ b/src/mainboard/google/veyron_mighty/romstage.c @@ -112,7 +112,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig index c3a47e54b0..0c991c7c28 100644 --- a/src/mainboard/google/veyron_pinky/Kconfig +++ b/src/mainboard/google/veyron_pinky/Kconfig @@ -68,10 +68,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 2048 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index ba96688705..74c5ef3585 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -120,7 +120,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 40b5c39d2e..8393895e16 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -64,10 +64,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 1024 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index c18471abe5..f3883bd28f 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -113,7 +113,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); diff --git a/src/mainboard/google/veyron_speedy/Kconfig b/src/mainboard/google/veyron_speedy/Kconfig index bbc3fc84ef..4d7f45d287 100644 --- a/src/mainboard/google/veyron_speedy/Kconfig +++ b/src/mainboard/google/veyron_speedy/Kconfig @@ -68,10 +68,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_SIZE_MB - int - default 2048 - config DRIVER_TPM_I2C_BUS hex default 0x1 diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c index c18471abe5..f3883bd28f 100644 --- a/src/mainboard/google/veyron_speedy/romstage.c +++ b/src/mainboard/google/veyron_speedy/romstage.c @@ -113,7 +113,7 @@ void main(void) /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, - CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); -- cgit v1.2.3