From ed7bb850310ec579db0b53a9dda4ad411c68f998 Mon Sep 17 00:00:00 2001
From: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Date: Fri, 29 May 2020 20:54:40 +0800
Subject: soc/mediatek/mt8192: add pmic MT6359P driver

MT6359P is a PMIC chipset for Mediatek MT8192 platform.
Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205.

BUG=b:155253454
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I62f69490165539847b8b7260942644533b15285b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45399
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/asurada/romstage.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/mainboard/google')

diff --git a/src/mainboard/google/asurada/romstage.c b/src/mainboard/google/asurada/romstage.c
index a0e0818e01..47c1fb2268 100644
--- a/src/mainboard/google/asurada/romstage.c
+++ b/src/mainboard/google/asurada/romstage.c
@@ -6,6 +6,7 @@
 #include <soc/dramc_param.h>
 #include <soc/emi.h>
 #include <soc/mmu_operations.h>
+#include <soc/mt6359p.h>
 
 /* This must be defined in chromeos.fmd in same name and size. */
 #define CALIBRATION_REGION		"RW_DDR_TRAINING"
@@ -43,6 +44,7 @@ static struct dramc_param_ops dparam_ops = {
 
 void platform_romstage_main(void)
 {
+	mt6359p_romstage_init();
 	mt_mem_init(&dparam_ops);
 	mtk_mmu_after_dram();
 }
-- 
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