From e608a4f4fd2a615f49c3bdafc2b4781be3efb103 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Mon, 18 Sep 2023 12:48:38 +0900 Subject: mb/google/nissa/var/pirrha: Add 4th DTT sensor Add 4th sensor device for DTT tuning. BUG=b:292134655 TEST=Built and verified DTT tool could monitor the new sensor device Change-Id: I62f50711af81dfc1566d655f6dcfc66f68dbc794 Signed-off-by: Seunghwan Kim Reviewed-on: https://review.coreboot.org/c/coreboot/+/77997 Tested-by: build bot (Jenkins) Reviewed-by: Derek Huang Reviewed-by: Shou-Chieh Hsu --- src/mainboard/google/brya/variants/pirrha/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/brya/variants/pirrha/overridetree.cb b/src/mainboard/google/brya/variants/pirrha/overridetree.cb index 81e6edb9f5..6ba61418c0 100644 --- a/src/mainboard/google/brya/variants/pirrha/overridetree.cb +++ b/src/mainboard/google/brya/variants/pirrha/overridetree.cb @@ -210,6 +210,7 @@ chip soc/intel/alderlake register "options.tsr[0].desc" = ""Memory"" register "options.tsr[1].desc" = ""Charger"" register "options.tsr[2].desc" = ""Ambient"" + register "options.tsr[3].desc" = ""Sub Charger"" # TODO: below values are initial reference values only ## Passive Policy @@ -218,6 +219,7 @@ chip soc/intel/alderlake [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000), }" ## Critical Policy @@ -226,6 +228,7 @@ chip soc/intel/alderlake [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), }" register "controls.power_limits" = "{ -- cgit v1.2.3