From dfe817e45165fdbb8f4f7f83de83710cc46e75d6 Mon Sep 17 00:00:00 2001
From: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Date: Tue, 22 Mar 2022 20:00:29 +0530
Subject: sc7280: Improve performance by removing delays in cpucp init

As cpucp prepare takes 300 msec moving to before ramstage

BUG=b:218406702
TEST=Validated on qualcomm sc7280 development board observed
total timestamp as 1.73 sec from 1.97 sec

Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb
Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
---
 src/mainboard/google/herobrine/romstage.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/mainboard/google')

diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c
index 2ea78b8f91..97ce5a7c77 100644
--- a/src/mainboard/google/herobrine/romstage.c
+++ b/src/mainboard/google/herobrine/romstage.c
@@ -5,6 +5,7 @@
 #include <soc/qclib_common.h>
 #include "board.h"
 #include <soc/shrm.h>
+#include <soc/cpucp.h>
 
 static void prepare_usb(void)
 {
@@ -18,6 +19,7 @@ static void prepare_usb(void)
 void platform_romstage_main(void)
 {
 	shrm_fw_load_reset();
+	cpucp_prepare();
 	/* QCLib: DDR init & train */
 	qclib_load_and_run();
 	prepare_usb();
-- 
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