From dee834aafcccf79f9d6c3319ead6212fced004a6 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 23 Sep 2021 13:23:37 -0600 Subject: mb/google/brya: Update PCH power cycle related durations The voltage rail discharge times have been measured, so therefore the boot time on a cold boot when the CSE must go through a global reset and thus a trip to S5 can be optimized. Select the lowest applicable value for each PchPmSlp UPD that can be used with these measurements. This is programmed in the baseboard because the measured discharge times leave (what should be) plenty of margin for variants to also not violate any power sequencing guidelines from the PDG. BUG=b:184799383 TEST=verified time in S5 during a global reset is ~1s instead of 4s Change-Id: Ia373c47b3967d68ddac21707c6eb4565d9d6519e Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/57892 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Nick Vaccaro --- src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 6f55770d2b..154f69799f 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -62,6 +62,12 @@ chip soc/intel/alderlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" + register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" + # HD Audio register "PchHdaDspEnable" = "1" register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" -- cgit v1.2.3