From da996f893d56a4a46ca1ba97bc9b46c00de1a5dc Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Thu, 4 Feb 2021 19:56:41 +0800 Subject: mb/google/zork: update USB 3 controller phy Parameter for dirinboz Recommendation from SOC to config IQ=8 for U3 port0, vboost for all U3 ports for passing ESD pin test. BUG=b:175192931 BRANCH=zork TEST=1. emerge-zork coreboot 2. run U3 SI/ESD pin test => pass Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/50282 Tested-by: build bot (Jenkins) Reviewed-by: Kangheui Won --- .../google/zork/variants/dirinboz/overridetree.cb | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index fc9c5fdfb0..1bfea1d1c4 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -60,6 +60,27 @@ chip soc/amd/picasso .tx_res_tune = 0x01, }" + # USB3 phy parameter + register "usb3_phy_override" = "1" + + # USB3 Port0 Default + register "usb3_phy_tune_params[0]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x8, + .rx_eq_delta_iq_ovrd_en = 0x1, + }" + + # SUP_DIG_LVL_OVRD_IN Default + register "usb3_rx_vref_ctrl" = "0x10" + register "usb3_rx_vref_ctrl_en" = "0x00" + register "usb_3_tx_vboost_lvl" = "0x07" + register "usb_3_tx_vboost_lvl_en" = "0x01" + + # SUPX_DIG_LVL_OVRD_IN Default + register "usb_3_rx_vref_ctrl_x" = "0x10" + register "usb_3_rx_vref_ctrl_en_x" = "0x00" + register "usb_3_tx_vboost_lvl_x" = "0x07" + register "usb_3_tx_vboost_lvl_en_x" = "0x01" + # I2C2 for touchscreen and trackpad register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, -- cgit v1.2.3