From d7de7bc1ee5d6a0e41ab54a9843448f651ed47e4 Mon Sep 17 00:00:00 2001 From: Gaggery Tsai Date: Wed, 20 Dec 2017 13:12:57 +0800 Subject: mb/google/fizz: revise LED0 behavior for link speed 100Mb This patch revises LED0 Green light behavior from patch 2ecf3f8c. For 100Mb link speed, LED0 should be OFF. BUG=b:65437780, b:68284778, b:69950854, b:65808944 BRANCH=None TEST=Run DUT with 100Mb and 1000Mb ethernet connection and observe LED0 is behaving as expected. Change-Id: Ia805c955711b8ce77eba087a28427a005c456fa1 Signed-off-by: Gaggery Tsai Reviewed-on: https://review.coreboot.org/22964 Reviewed-by: David Wu Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/fizz/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 59a80faa50..e94dd268d3 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -306,7 +306,7 @@ chip soc/intel/skylake device pci 19.2 off end # I2C #4 device pci 1c.0 on # PCI Express Port 1 chip drivers/net - register "customized_leds" = "0x0fa7" + register "customized_leds" = "0x0fa5" register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end @@ -326,7 +326,7 @@ chip soc/intel/skylake device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on # PCI Express Port 9 for 2nd LAN chip drivers/net - register "customized_leds" = "0x0fa7" + register "customized_leds" = "0x0fa5" device pci 00.0 on end end end # PCI Express Port 9 for BtoB -- cgit v1.2.3