From d5be4e4046a1ef89672f57e8c5674f95b66c97ae Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Fri, 3 Jan 2020 14:50:49 +0530
Subject: soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi

This patch creates a common instance of northbridge.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to
refer northbridge.asl from common code block.

TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
Device(MCHC) presence after booting to OS.

Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/dragonegg/dsdt.asl | 2 +-
 src/mainboard/google/drallion/dsdt.asl  | 2 +-
 src/mainboard/google/hatch/dsdt.asl     | 2 +-
 src/mainboard/google/sarien/dsdt.asl    | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/mainboard/google')

diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl
index 24814da9f8..f84b0b5a60 100644
--- a/src/mainboard/google/dragonegg/dsdt.asl
+++ b/src/mainboard/google/dragonegg/dsdt.asl
@@ -37,7 +37,7 @@ DefinitionBlock(
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include <soc/intel/icelake/acpi/northbridge.asl>
+			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 			#include <soc/intel/icelake/acpi/southbridge.asl>
 		}
 	}
diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl
index 78c6c16a33..ee63d6ee8a 100644
--- a/src/mainboard/google/drallion/dsdt.asl
+++ b/src/mainboard/google/drallion/dsdt.asl
@@ -36,7 +36,7 @@ DefinitionBlock(
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include <soc/intel/cannonlake/acpi/northbridge.asl>
+			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 			#include <soc/intel/cannonlake/acpi/southbridge.asl>
 		}
 		/* Per board variant mainboard hooks. */
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index 1a0ff68212..16a8a661b7 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -37,7 +37,7 @@ DefinitionBlock(
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include <soc/intel/cannonlake/acpi/northbridge.asl>
+			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 			#include <soc/intel/cannonlake/acpi/southbridge.asl>
 		}
 	}
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl
index a809b75e01..c32470eb1b 100644
--- a/src/mainboard/google/sarien/dsdt.asl
+++ b/src/mainboard/google/sarien/dsdt.asl
@@ -36,7 +36,7 @@ DefinitionBlock(
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include <soc/intel/cannonlake/acpi/northbridge.asl>
+			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 			#include <soc/intel/cannonlake/acpi/southbridge.asl>
 		}
 		/* Per board variant mainboard hooks. */
-- 
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