From c98df1478b7a00e1a56b421ced001f6876da07dd Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Tue, 11 Jan 2022 17:59:15 +0600 Subject: mb/google/brya/var/anahera{4es}: Set tcc_offset value to 3 The anahera thermal team has determined that the TCC circuit trip temperature should be set to 97C, therefore, because the offset is subtracted from 100C, set the `tcc_offset` register in the devicetree to 3. BUG=b:214088543 TEST=build and verified by thermal team Signed-off-by: Wisley Chen Change-Id: I25b8a3d9e5fe28e9497b735c50a09994092b2243 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61002 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/anahera/overridetree.cb | 1 + src/mainboard/google/brya/variants/anahera4es/overridetree.cb | 1 + 2 files changed, 2 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index c9b3bd8045..e670f4a0da 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -62,6 +62,7 @@ chip soc/intel/alderlake .data_hold_time_ns = 50, }, }" + register "tcc_offset" = "3" # TCC of 97C register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index 0b6db9f95e..e04ff886a7 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -54,6 +54,7 @@ chip soc/intel/alderlake .speed = I2C_SPEED_FAST, }, }" + register "tcc_offset" = "3" # TCC of 97C register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port -- cgit v1.2.3