From c94631718b16e027e7ab80006dca494bdb52bb63 Mon Sep 17 00:00:00 2001 From: John Su Date: Thu, 14 Feb 2019 17:24:17 +0800 Subject: mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1 Follow b:123461432#5 to update GPIO H3(CNVI_EN#) for DVT1. Update setting GPIO H3 to output and low level. BUG=b:123461432 TEST=Built and tested on sarien system Change-Id: I6a56df9a7bf75f49133a646312ae5093c2652698 Signed-off-by: John Su Reviewed-on: https://review.coreboot.org/c/31412 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/mainboard/google/sarien/variants/sarien/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index e735fee2f2..ff311b1293 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -188,7 +188,7 @@ static const struct pad_config gpio_table[] = { /* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), /* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ /* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ -/* I2S2_RXD */ PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* CNVI_EN# */ +/* I2S2_RXD */ PAD_CFG_GPO(GPP_H3, 0, DEEP), /* CNVI_EN# */ /* I2C2_SDA */ PAD_NC(GPP_H4, NONE), /* T388 */ /* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* T389 */ /* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* T378 */ -- cgit v1.2.3