From c8d45ac88e0c1170bb1b8b01a52701d96416e626 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 6 Jun 2016 17:21:00 -0700 Subject: skylake: Move I2C bus configuration to separate structure Move the existing I2C voltage configuration variable into a new structure that is equivalent, similar to how USB ports are configured. This is to make room for additional I2C configuration options like bus speed and whether to enable the bus in early boot which are coming in a subsequent commit. The affected mainboards are updated in this commit so it will build. Signed-off-by: Duncan Laurie Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e Reviewed-on: https://review.coreboot.org/15104 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/mainboard/google/chell/devicetree.cb | 5 ++--- src/mainboard/google/glados/devicetree.cb | 5 ++--- src/mainboard/google/lars/devicetree.cb | 3 ++- 3 files changed, 6 insertions(+), 7 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 428779a470..349f724cf3 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -153,6 +153,8 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # SD + register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -168,9 +170,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - # I2C4 is 1.8V - register "SerialIoI2cVoltage[4]" = "1" - # PL2 override 15W register "tdp_pl2_override" = "15" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index c4b89af4aa..6518dbfdb2 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -153,6 +153,8 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port 1 register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port 2 + register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -168,9 +170,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoPci, }" - # I2C4 is 1.8V - register "SerialIoI2cVoltage[4]" = "1" - # PL2 override 15W register "tdp_pl2_override" = "15" diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index 5607ec83a4..fce0495a2f 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -149,7 +149,8 @@ chip soc/intel/skylake register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # SD register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card) register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board) - register "SerialIoI2cVoltage[4]" = "1" # I2C4 is 1.8V + + register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \ -- cgit v1.2.3