From c70eed1e6202c928803f3e7f79161cd247a62b23 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 22 May 2018 02:18:00 +0300 Subject: device: Use pcidev_on_root() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) Reviewed-by: Piotr Król Reviewed-by: Arthur Heymans --- src/mainboard/google/kahlee/mptable.c | 2 +- src/mainboard/google/link/mainboard.c | 2 +- src/mainboard/google/link/romstage.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c index 0cda7f7676..428e5751f8 100644 --- a/src/mainboard/google/kahlee/mptable.c +++ b/src/mainboard/google/kahlee/mptable.c @@ -113,7 +113,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 4919e6baed..6c896fcc55 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -151,7 +151,7 @@ static void mainboard_init(struct device *dev) /* If running on proto1 - enable reversion of gpio11. */ u32 gpio_inv; u16 gpio_base = pci_read_config16 - (dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE) & + (pcidev_on_root(0x1f, 0), GPIO_BASE) & 0xfffc; u16 gpio_inv_addr = gpio_base + GPI_INV; gpio_inv = inl(gpio_inv_addr); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index b8c13a1a19..73d33a3a12 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -39,7 +39,7 @@ void pch_enable_lpc(void) const struct device *lpc; const struct southbridge_intel_bd82x6x_config *config = NULL; - lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + lpc = pcidev_on_root(0x1f, 0); if (!lpc) return; if (lpc->chip_info) -- cgit v1.2.3