From c5a7d604c8e61cfc482cd7cb1f4d186d1dddef8f Mon Sep 17 00:00:00 2001 From: Sukumar Ghorai Date: Mon, 31 Jul 2023 18:11:04 -0700 Subject: mb/google/rex: enable d3hot for storage devices _DSD "StorageD3Enable" property is needs to be set under the root port in the DSDT or SSDT. The ACPI _DSD method is the preferred way to opt D3hot support for storage devices. This also bypasses the low LTR from SSD that blocking S0i2.2 LTR/latency SoC requirement. Name (_DSD, Package () { ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"), Package () { Package (2) {"StorageD3Enable", 1}, // 1 - Enable; 0 - Disable } } ) BUG=b:289028958 TEST=Check code compiles & boot rex, and verify the "StorageD3Enable" SSDT entry. Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7 Signed-off-by: Kangheui Won Signed-off-by: Sukumar Ghorai Reviewed-on: https://review.coreboot.org/c/coreboot/+/76835 Reviewed-by: Sumeet R Pawnikar Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- src/mainboard/google/rex/variants/rex0/overridetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 0cbea7b052..5c7958a72f 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -303,6 +303,13 @@ chip soc/intel/meteorlake .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A19)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)" + register "srcclk_pin" = "4" + device generic 0 on end + end end #PCIE9 SSD card device ref ish on probe ISH ISH_ENABLE -- cgit v1.2.3