From c4a3f51618a7575628fb513133952ac57326fc24 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Tue, 24 Dec 2019 14:11:43 +1100 Subject: mainboard/google/hatch: Move gpio GPP_A* NC down into baseboard The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_A* group for easier review. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: I29b4323ac80b1288b2562846217c4f377714fc2c Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37920 Tested-by: build bot (Jenkins) Reviewed-by: Kangheui Won Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/akemi/gpio.c | 24 --------------- .../google/hatch/variants/baseboard/gpio.c | 24 +++++++-------- src/mainboard/google/hatch/variants/dratini/gpio.c | 12 +++----- src/mainboard/google/hatch/variants/hatch/gpio.c | 12 ++++++++ src/mainboard/google/hatch/variants/helios/gpio.c | 12 +++++--- src/mainboard/google/hatch/variants/jinlon/gpio.c | 12 +++----- src/mainboard/google/hatch/variants/kindred/gpio.c | 36 ++++++++++++++++++++++ src/mainboard/google/hatch/variants/kohaku/gpio.c | 12 ++++---- src/mainboard/google/hatch/variants/mushu/gpio.c | 12 ++++++++ src/mainboard/google/hatch/variants/stryke/gpio.c | 12 -------- 10 files changed, 94 insertions(+), 74 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 0780ddb97a..41cf1410bc 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -19,18 +19,6 @@ #include static const struct pad_config ssd_sku_gpio_table[] = { - /* A0 : NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : NC */ - PAD_NC(GPP_A6, NONE), - /* A8 : NC */ - PAD_NC(GPP_A8, NONE), - /* A10 : NC */ - PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), - /* A12 : NC */ - PAD_NC(GPP_A12, NONE), /* A18 : NC */ PAD_NC(GPP_A18, NONE), /* A19 : NC */ @@ -90,18 +78,6 @@ static const struct pad_config ssd_sku_gpio_table[] = { }; static const struct pad_config gpio_table[] = { - /* A0 : NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : NC */ - PAD_NC(GPP_A6, NONE), - /* A8 : NC */ - PAD_NC(GPP_A8, NONE), - /* A10 : NC */ - PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), - /* A12 : NC */ - PAD_NC(GPP_A12, NONE), /* A18 : NC */ PAD_NC(GPP_A18, NONE), /* A19 : NC */ diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 94cb2e53a2..42e9501d01 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -19,26 +19,26 @@ #include static const struct pad_config gpio_table[] = { - /* A0 : SAR0_INT_ODL */ - PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), + /* A0 : GPP_A0 ==> NC */ + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ - /* A6 : SAR1_INT_ODL */ - PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), + /* A6 : GPP_A6 ==> NC */ + PAD_NC(GPP_A6, NONE), /* A7 : PP3300_SOC_A */ PAD_NC(GPP_A7, NONE), - /* A8 : PEN_GARAGE_DET_L (wake) */ - PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A8 : GPP_A8 ==> NC */ + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ - /* A10 : FPMCU_PCH_BOOT1 */ - PAD_CFG_GPO(GPP_A10, 0, DEEP), - /* A11 : PCH_SPI_FPMCU_CS_L */ - PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* A10 : GPP_A10 ==> NC */ + PAD_NC(GPP_A10, NONE), + /* A11 : GPP_A11 ==> NC */ + PAD_NC(GPP_A11, NONE), + /* A12 : GPP_A12 ==> NC */ + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RST_L */ diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 30d56d78b8..b61748b268 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -19,14 +19,10 @@ #include static const struct pad_config gpio_table[] = { - /* A0 : NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : NC */ - PAD_NC(GPP_A6, NONE), - /* A8 : NC */ - PAD_NC(GPP_A8, NONE), - /* A10 : NC */ - PAD_NC(GPP_A10, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* A18 : NC */ PAD_NC(GPP_A18, NONE), /* A19 : NC */ diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 56f587b6b8..a2adf25371 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -19,6 +19,18 @@ #include static const struct pad_config gpio_table[] = { + /* A0 : SAR0_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), + /* A6 : SAR1_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* C13 : EC_PCH_INT_L */ PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index 456877c8ee..86630996e7 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -19,10 +19,14 @@ #include static const struct pad_config gpio_table[] = { - /* A0 : RCIN# ==> NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : SERIRQ ==> NC */ - PAD_NC(GPP_A6, NONE), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* A18 : ISH_GP0 ==> NC */ PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 4622a72740..3cf2c9d13e 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -19,14 +19,10 @@ #include static const struct pad_config gpio_table[] = { - /* A0 : NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : NC */ - PAD_NC(GPP_A6, NONE), - /* A8 : NC */ - PAD_NC(GPP_A8, NONE), - /* A10 : NC */ - PAD_NC(GPP_A10, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* C12 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_C12, 0, DEEP), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index 9e2d818f9b..3c542437d6 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -19,6 +19,18 @@ #include static const struct pad_config ssd_sku_gpio_table[] = { + /* A0 : SAR0_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), + /* A6 : SAR1_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ @@ -54,6 +66,18 @@ static const struct pad_config ssd_sku_gpio_table[] = { }; static const struct pad_config emmc_sku_gpio_table[] = { + /* A0 : SAR0_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), + /* A6 : SAR1_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* E1 : M2_SSD_PEDET ==> NC */ PAD_NC(GPP_E1, NONE), /* E4 : M2_SSD_PE_WAKE_ODL ==> NC */ @@ -95,6 +119,18 @@ static const struct pad_config emmc_sku_gpio_table[] = { }; static const struct pad_config gpio_table[] = { + /* A0 : SAR0_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), + /* A6 : SAR1_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index f52cc27724..837abb3e8b 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -19,12 +19,12 @@ #include static const struct pad_config gpio_table[] = { - /* A0 : RCIN# ==> NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : SERIRQ ==> NC */ - PAD_NC(GPP_A6, NONE), - /* A10 : GPP_A10 ==> NC */ - PAD_NC(GPP_A10, NONE), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* A16 : EMR_GARAGE_DET (notification) */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A16, NONE, PLTRST), /* A17 : PIRQA# ==> NC */ diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index 56f587b6b8..a2adf25371 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -19,6 +19,18 @@ #include static const struct pad_config gpio_table[] = { + /* A0 : SAR0_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), + /* A6 : SAR1_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* C13 : EC_PCH_INT_L */ PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index 4d27554a6b..4fdbe6aa39 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -19,18 +19,6 @@ #include static const struct pad_config gpio_table[] = { - /* A0 : NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : NC */ - PAD_NC(GPP_A6, NONE), - /* A8 : NC */ - PAD_NC(GPP_A8, NONE), - /* A10 : NC */ - PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), - /* A12 : NC */ - PAD_NC(GPP_A12, NONE), /* A22 : NC */ PAD_NC(GPP_A22, NONE), /* A23 : NC */ -- cgit v1.2.3