From bfd17e34219f71e3cca458648997cb2f8f5ee2ca Mon Sep 17 00:00:00 2001
From: Duncan Laurie <dlaurie@google.com>
Date: Thu, 26 Oct 2017 08:44:16 -0700
Subject: mb/google/eve: Tune I2C4 hold times

Tune PCH I2C4 hold times to ensure the frequency is always <400KHz.

BUG=b:67029862
TEST=boot on eve and measure I2C4 at Tp262 to be 385KHz

Change-Id: Ie93c5c40bc74069b285f6c3ee311f1bd7cefcaf1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Iceabc806a17b9e6a144a4f6288c6cca790d03950
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/739841
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/mainboard/google/eve/devicetree.cb | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'src/mainboard/google')

diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 3b87fd17b5..50926da29a 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -198,8 +198,12 @@ chip soc/intel/skylake
 	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
 	register "i2c[4]" = "{
 		.speed = I2C_SPEED_FAST,
-		.rise_time_ns = 240,
-		.fall_time_ns = 30,
+		.speed_config[0] = {
+			.speed = I2C_SPEED_FAST,
+			.scl_lcnt = 176,
+			.scl_hcnt = 95,
+			.sda_hold = 36,
+		}
 	}"
 
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
-- 
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