From be426e0722be270916cadd2098b2224a6fa5ec00 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Tue, 27 Feb 2024 16:12:05 +0900 Subject: mb/google/brya/var/xol: Add storage option in FW_CONFIG Add STORAGE config in FW_CONFIG to support NVME sku. - STORAGE_UFS : 0 - STORAGE_NVME: 1 BUG=b:326481458 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: Id8316f643ba9a55319b67431a24a507e92419aa7 Signed-off-by: Seunghwan Kim Reviewed-on: https://review.coreboot.org/c/coreboot/+/80767 Reviewed-by: Kapil Porwal Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/google/brya/variants/xol/overridetree.cb | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index 8ace1e7637..f840afed9e 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -1,3 +1,9 @@ +fw_config + field STORAGE 0 0 + option STORAGE_UFS 0 + option STORAGE_NVME 1 + end +end chip soc/intel/alderlake register "domain_vr_config[VR_DOMAIN_IA]" = "{ @@ -261,7 +267,8 @@ chip soc/intel/alderlake .clk_src = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - end # SSD + probe STORAGE STORAGE_NVME + end # NVMe device ref tbt_pcie_rp0 off end device ref tbt_pcie_rp1 off end device ref tbt_pcie_rp2 off end @@ -273,8 +280,11 @@ chip soc/intel/alderlake register "add_acpi_dma_property" = "true" device generic 0 on end end + probe STORAGE STORAGE_UFS + end + device ref ufs on + probe STORAGE STORAGE_UFS end - device ref ufs on end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" -- cgit v1.2.3