From be23f04ce7ccad902c92766b29abd1577482ec61 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 15 Feb 2024 15:36:15 -0600 Subject: soc/intel/cannonlake: select SOC_INTEL_COMMON_BLOCK_DTT Select this at the SoC level (like other modern Intel SoCs), and drop it from individual boards which selected it. Change-Id: I838ada7dfe948c58a5bb9805ade289b07368aa63 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/80556 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Eric Lai Reviewed-by: Felix Singer --- src/mainboard/google/hatch/Kconfig | 1 - src/mainboard/google/puff/Kconfig | 1 - 2 files changed, 2 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 32ce7ed045..493db33902 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -26,7 +26,6 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select MAINBOARD_HAS_TPM2 select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SOC_INTEL_COMETLAKE_1 - select SOC_INTEL_COMMON_BLOCK_DTT select SPI_TPM select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig index 348aa1e14e..0abe53a10e 100644 --- a/src/mainboard/google/puff/Kconfig +++ b/src/mainboard/google/puff/Kconfig @@ -31,7 +31,6 @@ config BOARD_GOOGLE_BASEBOARD_PUFF select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select SOC_INTEL_COMETLAKE_1 - select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_CSE_LITE_SKU select SPD_CACHE_IN_FMAP select SPD_READ_BY_WORD -- cgit v1.2.3