From ba26aa8981b403927c921c09419579d4f57140be Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Wed, 24 Jun 2020 14:26:03 +0800 Subject: mb/google/faffy: Enable USB2 port6 Due to faffy has PL-2303 connect to USB2 port6(count from port0), needs to enable it. BUG=b:159760559 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage boot on puff board Change-Id: Icc805757b043e7fac4d05188cbf2f9c9c56c2a2e Signed-off-by: Tim Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/42766 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/mainboard/google/hatch/variants/faffy/overridetree.cb | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb index 55ce5ea084..ffb9cb3317 100644 --- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb @@ -62,7 +62,14 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # PL2303 register "usb2_ports[7]" = "USB2_PORT_EMPTY" register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ -- cgit v1.2.3