From b91e5180626bcbb90fe69f23c08511aeff58c5d7 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Fri, 28 Aug 2020 11:56:31 +0800 Subject: mb/google/zork: update GPIO config for dirinboz dirinboz does not support stylus, config AGPIO4/5 to NC to prevent unexpected wake event for s3. BUG=none BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Change-Id: I3cfdeb326c3d3775148b2a00732c7d848dab35cb Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/44894 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/zork/variants/dirinboz/gpio.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/zork/variants/dirinboz/gpio.c b/src/mainboard/google/zork/variants/dirinboz/gpio.c index 12b303a9c5..8da85b6720 100644 --- a/src/mainboard/google/zork/variants/dirinboz/gpio.c +++ b/src/mainboard/google/zork/variants/dirinboz/gpio.c @@ -8,6 +8,10 @@ #include static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), /* TP */ PAD_NC(GPIO_32), /* EN_DEV_BEEP_L */ @@ -16,6 +20,13 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { PAD_GPO(GPIO_140, HIGH), }; +static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version; @@ -33,6 +44,6 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) return bid_1_gpio_set_stage_ram; } - *size = 0; - return NULL; + *size = ARRAY_SIZE(dirinboz_gpio_set_stage_ram); + return dirinboz_gpio_set_stage_ram; } -- cgit v1.2.3