From b7b11475c16b658698d1adcc9dbc0d969eddb9bd Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 6 Jan 2020 23:40:59 -0700 Subject: mb/google/dedede: Enable building for Chrome OS Enable building for Chrome OS and add associated ACPI configuration. BUG=b:144768001 TEST=Build Test Change-Id: Ibb94849a903e4d4364d817de8988a430cd717e4c Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/38281 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/dedede/Kconfig | 6 +++ src/mainboard/google/dedede/Makefile.inc | 6 +++ src/mainboard/google/dedede/chromeos.c | 51 ++++++++++++++++++++++ src/mainboard/google/dedede/dsdt.asl | 3 ++ src/mainboard/google/dedede/mainboard.c | 3 +- .../google/dedede/variants/baseboard/gpio.c | 10 +++++ .../baseboard/include/baseboard/variants.h | 1 + 7 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/google/dedede/chromeos.c (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 21ba001757..cc7aff6ac1 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_JASPERLAKE if BOARD_GOOGLE_BASEBOARD_DEDEDE @@ -10,6 +11,11 @@ config BASEBOARD_DEDEDE_LAPTOP def_bool n select SYSTEM_TYPE_LAPTOP +config CHROMEOS + bool + default y + select VBOOT_LID_SWITCH + config DEVICETREE string default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc index f214544e09..5cb209da8a 100644 --- a/src/mainboard/google/dedede/Makefile.inc +++ b/src/mainboard/google/dedede/Makefile.inc @@ -1,5 +1,11 @@ bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c new file mode 100644 index 0000000000..44a8c042a8 --- /dev/null +++ b/src/mainboard/google/dedede/chromeos.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_lid_switch(void) +{ + /* TODO: use Chrome EC switches when EC support is added */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + /* TODO: use Chrome EC switches when EC support is added */ + return 0; +} + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index c387fd38d7..3e278e3e9d 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -35,6 +35,9 @@ DefinitionBlock( } } + /* Chrome OS specific */ + #include + /* Chipset specific sleep states */ #include diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index b663a43071..64bb5ac824 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -9,6 +9,7 @@ #include #include #include +#include static void mainboard_init(void *chip_info) { @@ -28,7 +29,7 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt_generator = NULL; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 65ac66b319..6c95a1d0f0 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -9,6 +9,7 @@ #include #include #include +#include /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { @@ -41,3 +42,12 @@ const struct pad_config *__weak variant_sleep_gpio_table(size_t *num) *num = ARRAY_SIZE(sleep_gpio_table); return sleep_gpio_table; } + +static const struct cros_gpio cros_gpios[] = { +}; + +const struct cros_gpio *__weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index 309b9ebc5d..d7c482c172 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -18,5 +18,6 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_sleep_gpio_table(size_t *num); +const struct cros_gpio *variant_cros_gpios(size_t *num); #endif /*__BASEBOARD_VARIANTS_H__ */ -- cgit v1.2.3