From b30a47b841f1c7d55d9cf207e1cc89f1b7f7fa51 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 15 Jul 2019 18:04:23 +0200 Subject: sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supported The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/mainboard/google/butterfly/devicetree.cb | 1 - src/mainboard/google/link/devicetree.cb | 1 - src/mainboard/google/parrot/devicetree.cb | 1 - src/mainboard/google/stout/devicetree.cb | 1 - 4 files changed, 4 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index d8a0ee1c31..3c08b8bb60 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 1b27a69b54..ec7fb201d7 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -64,7 +64,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 046db97585..33d3544264 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -62,7 +62,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index ddcf4e22d1..b9ccbf938c 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -73,7 +73,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 -- cgit v1.2.3