From af69de494e2c32140ce5e00a1562c2845345b1bf Mon Sep 17 00:00:00 2001 From: Isaac Lee Date: Thu, 26 Jan 2023 16:06:19 -0800 Subject: mb/google/skyrim: Create whiterun variant Create the whiterun variant of the skyrim reference board by copying the winterhold files to a new directory named for the variant. BUG=b:265955979 BRANCH=None TEST=emerge-skyrim coreboot and boot up on Whiterun Change-Id: I3539f84e79c05936fe006bfe9d08743d6a9a6ba7 Signed-off-by: Isaac Lee Reviewed-on: https://review.coreboot.org/c/coreboot/+/72483 Reviewed-by: Martin L Roth Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- src/mainboard/google/skyrim/Kconfig | 2 + src/mainboard/google/skyrim/Kconfig.name | 6 + .../google/skyrim/variants/whiterun/Makefile.inc | 5 + .../google/skyrim/variants/whiterun/gpio.c | 28 +++ .../whiterun/include/variant/acpi/dtts.asl | 116 +++++++++ .../skyrim/variants/whiterun/include/variant/ec.h | 3 + .../skyrim/variants/whiterun/memory/Makefile.inc | 14 ++ .../variants/whiterun/memory/dram_id.generated.txt | 21 ++ .../variants/whiterun/memory/mem_parts_used.txt | 15 ++ .../skyrim/variants/whiterun/overridetree.cb | 271 +++++++++++++++++++++ 10 files changed, 481 insertions(+) create mode 100644 src/mainboard/google/skyrim/variants/whiterun/Makefile.inc create mode 100644 src/mainboard/google/skyrim/variants/whiterun/gpio.c create mode 100644 src/mainboard/google/skyrim/variants/whiterun/include/variant/acpi/dtts.asl create mode 100644 src/mainboard/google/skyrim/variants/whiterun/include/variant/ec.h create mode 100644 src/mainboard/google/skyrim/variants/whiterun/memory/Makefile.inc create mode 100644 src/mainboard/google/skyrim/variants/whiterun/memory/dram_id.generated.txt create mode 100644 src/mainboard/google/skyrim/variants/whiterun/memory/mem_parts_used.txt create mode 100644 src/mainboard/google/skyrim/variants/whiterun/overridetree.cb (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index 092cd55638..13fb8048b0 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -98,6 +98,7 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER default "Skyrim" if BOARD_GOOGLE_SKYRIM + default "Whiterun" if BOARD_GOOGLE_WHITERUN default "Winterhold" if BOARD_GOOGLE_WINTERHOLD default "Frostflow" if BOARD_GOOGLE_FROSTFLOW default "Crystaldrift" if BOARD_GOOGLE_CRYSTALDRIFT @@ -110,6 +111,7 @@ config OVERRIDE_DEVICETREE config VARIANT_DIR string default "skyrim" if BOARD_GOOGLE_SKYRIM + default "whiterun" if BOARD_GOOGLE_WHITERUN default "winterhold" if BOARD_GOOGLE_WINTERHOLD default "frostflow" if BOARD_GOOGLE_FROSTFLOW default "crystaldrift" if BOARD_GOOGLE_CRYSTALDRIFT diff --git a/src/mainboard/google/skyrim/Kconfig.name b/src/mainboard/google/skyrim/Kconfig.name index 7e458770e5..18277603cd 100644 --- a/src/mainboard/google/skyrim/Kconfig.name +++ b/src/mainboard/google/skyrim/Kconfig.name @@ -5,6 +5,12 @@ config BOARD_GOOGLE_SKYRIM select BOARD_GOOGLE_BASEBOARD_SKYRIM select SOC_AMD_COMMON_BLOCK_ACPI_DPTC +config BOARD_GOOGLE_WHITERUN + bool "-> Whiterun" + select BOARD_GOOGLE_BASEBOARD_SKYRIM + select SOC_AMD_COMMON_BLOCK_ACPI_DPTC + select FEATURE_DYNAMIC_DPTC + config BOARD_GOOGLE_WINTERHOLD bool "-> Winterhold" select BOARD_GOOGLE_BASEBOARD_SKYRIM diff --git a/src/mainboard/google/skyrim/variants/whiterun/Makefile.inc b/src/mainboard/google/skyrim/variants/whiterun/Makefile.inc new file mode 100644 index 0000000000..db72b152a7 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/whiterun/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./memory + +ramstage-y += gpio.c diff --git a/src/mainboard/google/skyrim/variants/whiterun/gpio.c b/src/mainboard/google/skyrim/variants/whiterun/gpio.c new file mode 100644 index 0000000000..340bfb6fd2 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/whiterun/gpio.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include +#include +#include +#include + +/* GPIO configuration in ramstage */ +static const struct soc_amd_gpio override_gpio_table[] = { + + /* SOC_PEN_DETECT_ODL */ + PAD_NC(GPIO_3), + + /* EN_PWR_WWAN_X */ + PAD_NC(GPIO_8), + + /* SD_AUX_RST_SOC_L */ + PAD_NC(GPIO_27), + + /* WWAN_RST_L */ + PAD_NC(GPIO_42), + +}; + +void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(override_gpio_table); + *gpio = override_gpio_table; +} diff --git a/src/mainboard/google/skyrim/variants/whiterun/include/variant/acpi/dtts.asl b/src/mainboard/google/skyrim/variants/whiterun/include/variant/acpi/dtts.asl new file mode 100644 index 0000000000..9bac487cd7 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/whiterun/include/variant/acpi/dtts.asl @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +External(\_SB.DTTB, MethodObj) +External(\_SB.DTTC, MethodObj) +External(\_SB.DTTD, MethodObj) +External(\_SB.DTTE, MethodObj) +External(\_SB.DTTF, MethodObj) + +Scope (\_SB) +{ + //--------------------------------------------- + // Table | A | B | C | D | E | F | First boot | + //--------------------------------------------- + // PRTN | 0 | 1 | 2 | 3 | 4 | 5 | 7 | + //--------------------------------------------- + Name (PRTN, 7) + + Method (DTTS, 0, Serialized) + { + // Set table A as default table after power on device + If (\_SB.PRTN == 7) + { + \_SB.DDEF() + \_SB.PRTN = 0 + Return (0) + } + + If (\_SB.PCI0.LPCB.EC0.STTB == 0) { // Desktop + If (\_SB.PCI0.LPCB.EC0.LIDS == 1) { // Lid-open + // Table A/B + If ((\_SB.PRTN == 0) || (\_SB.PRTN == 1)) { + // AMB sensor trigger point + // 50C will store 123(0x7B) in mapped memory + // 50C=323K, 323-200(offset)=123(0x7B) + If (\_SB.PCI0.LPCB.EC0.TIN4 >= 123) { + \_SB.DTTB() + \_SB.PRTN = 1 + Return (0) + } + // AMB sensor release point + If ((\_SB.PCI0.LPCB.EC0.TIN4 <= 118)) { + \_SB.DDEF() + \_SB.PRTN = 0 + Return (0) + } + // Keep tht previous thermal table + Return (0) + } Else { + If (\_SB.PRTN == 3 || \_SB.PRTN == 5) { + \_SB.DTTB() + \_SB.PRTN = 1 + Return (0) + } Else { + \_SB.DDEF() + \_SB.PRTN = 0 + Return (0) + } + } + } Else { // Lid-close + // Table C/D + If (\_SB.PRTN == 2 || \_SB.PRTN == 3) { + If (\_SB.PCI0.LPCB.EC0.TIN4 >= 128) { + \_SB.DTTD() + \_SB.PRTN = 3 + Return (0) + } + If(\_SB.PCI0.LPCB.EC0.TIN4 <= 123) { + \_SB.DTTC() + \_SB.PRTN = 2 + Return (0) + } + // Keep tht previous thermal table + Return (0) + } Else { + If (\_SB.PRTN == 1 || \_SB.PRTN == 5) { + \_SB.DTTD() + \_SB.PRTN = 3 + Return (0) + } Else { + \_SB.DTTC() + \_SB.PRTN = 2 + Return (0) + } + } + } + } Else { // Laptop + // Table E/F + If (\_SB.PRTN == 4 || \_SB.PRTN == 5) { + // AMB sensor trigger point + If (\_SB.PCI0.LPCB.EC0.TIN4 >= 118) { + \_SB.DTTF() + \_SB.PRTN = 5 + Return (0) + } + // AMB sensor release point + If ((\_SB.PCI0.LPCB.EC0.TIN4 <= 113)) { + \_SB.DTTE() + \_SB.PRTN = 4 + Return (0) + } + // Keep tht previous thermal table + Return (0) + } Else { + If (\_SB.PRTN == 1 || \_SB.PRTN == 3) { + \_SB.DTTF() + \_SB.PRTN = 5 + Return (0) + } Else { + \_SB.DTTE() + \_SB.PRTN = 4 + Return (0) + } + } + } // Desktop/Laptop End + } +} diff --git a/src/mainboard/google/skyrim/variants/whiterun/include/variant/ec.h b/src/mainboard/google/skyrim/variants/whiterun/include/variant/ec.h new file mode 100644 index 0000000000..9e61a440cf --- /dev/null +++ b/src/mainboard/google/skyrim/variants/whiterun/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/skyrim/variants/whiterun/memory/Makefile.inc b/src/mainboard/google/skyrim/variants/whiterun/memory/Makefile.inc new file mode 100644 index 0000000000..d352edb53f --- /dev/null +++ b/src/mainboard/google/skyrim/variants/whiterun/memory/Makefile.inc @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen MDN lp5 src/mainboard/google/skyrim/variants/whiterun/memory src/mainboard/google/skyrim/variants/whiterun/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-1/spd-5.hex # ID = 0(0b0000) Parts = K3LKLKL0EM-MGCN +SPD_SOURCES += spd/lp5/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-1/spd-3.hex # ID = 2(0b0010) Parts = K3LKBKB0BM-MGCP, H58G56AK6BX069 +SPD_SOURCES += spd/lp5/set-1/spd-2.hex # ID = 3(0b0011) Parts = MT62F1G32D4DR-031 WT:B +SPD_SOURCES += spd/lp5/set-1/spd-7.hex # ID = 4(0b0100) Parts = MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, H58G56BK7BX068 +SPD_SOURCES += spd/lp5/set-1/spd-6.hex # ID = 5(0b0101) Parts = K3LKCKC0BM-MGCP, H58G66AK6BX070 +SPD_SOURCES += spd/lp5/set-1/spd-4.hex # ID = 6(0b0110) Parts = MT62F2G32D8DR-031 WT:B +SPD_SOURCES += spd/lp5/set-1/spd-8.hex # ID = 7(0b0111) Parts = MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT, H58G66BK7BX067 diff --git a/src/mainboard/google/skyrim/variants/whiterun/memory/dram_id.generated.txt b/src/mainboard/google/skyrim/variants/whiterun/memory/dram_id.generated.txt new file mode 100644 index 0000000000..107147e053 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/whiterun/memory/dram_id.generated.txt @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen MDN lp5 src/mainboard/google/skyrim/variants/whiterun/memory src/mainboard/google/skyrim/variants/whiterun/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +K3LKLKL0EM-MGCN 0 (0000) +MT62F512M32D2DR-031 WT:B 1 (0001) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3LKBKB0BM-MGCP 2 (0010) +H58G56AK6BX069 2 (0010) +MT62F1G32D4DR-031 WT:B 3 (0011) +MT62F1G32D2DS-026 WT:B 4 (0100) +K3KL8L80CM-MGCT 4 (0100) +K3LKCKC0BM-MGCP 5 (0101) +H58G66AK6BX070 5 (0101) +MT62F2G32D8DR-031 WT:B 6 (0110) +MT62F2G32D4DS-026 WT:B 7 (0111) +K3KL9L90CM-MGCT 7 (0111) +H58G56BK7BX068 4 (0100) +H58G66BK7BX067 7 (0111) diff --git a/src/mainboard/google/skyrim/variants/whiterun/memory/mem_parts_used.txt b/src/mainboard/google/skyrim/variants/whiterun/memory/mem_parts_used.txt new file mode 100644 index 0000000000..eda02b88c2 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/whiterun/memory/mem_parts_used.txt @@ -0,0 +1,15 @@ +K3LKLKL0EM-MGCN, +MT62F512M32D2DR-031 WT:B, +H9JCNNNBK3MLYR-N6E, +K3LKBKB0BM-MGCP, +H58G56AK6BX069, +MT62F1G32D4DR-031 WT:B, +MT62F1G32D2DS-026 WT:B, +K3KL8L80CM-MGCT, +K3LKCKC0BM-MGCP, +H58G66AK6BX070, +MT62F2G32D8DR-031 WT:B, +MT62F2G32D4DS-026 WT:B, +K3KL9L90CM-MGCT, +H58G56BK7BX068, +H58G66BK7BX067, diff --git a/src/mainboard/google/skyrim/variants/whiterun/overridetree.cb b/src/mainboard/google/skyrim/variants/whiterun/overridetree.cb new file mode 100644 index 0000000000..04da26c62e --- /dev/null +++ b/src/mainboard/google/skyrim/variants/whiterun/overridetree.cb @@ -0,0 +1,271 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/amd/mendocino + + # Set DPTC multi-profile common parameters + + # Refer the spec "FT6 Infrastructure Roadmap"#57316 + # Set system_configuration to 4 for 15W + register "system_configuration" = "4" + register "thermctl_limit_degreeC" = "97" + + register "stt_control" = "1" + register "stt_pcb_sensor_count" = "2" + register "stt_alpha_apu" = "0x199A" + register "stt_error_coeff" = "0x21" + register "stt_error_rate_coefficient" = "0xCCD" + + # These registers are defined in AMD DevHub document #57316. + # Normal + register "vrm_current_limit_mA" = "28000" + register "vrm_maximum_current_limit_mA" = "50000" + register "vrm_soc_current_limit_mA" = "10000" + # Throttle (e.g., Low/No Battery) + register "vrm_current_limit_throttle_mA" = "20000" + register "vrm_maximum_current_limit_throttle_mA" = "20000" + register "vrm_soc_current_limit_throttle_mA" = "10000" + + # Set Dynamic DPTC thermal profile Table A (Default) + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_limit_mW" = "18000" + register "slow_ppt_time_constant_s" = "7" + register "sustained_power_limit_mW" = "15000" + + register "stt_min_limit" = "7000" + register "stt_m1" = "0x148" + register "stt_m2" = "0x38F" + register "stt_c_apu" = "0xDF9A" + register "stt_skin_temp_apu" = "0x3200" + + # Set Dynamic DPTC thermal profile confiuration. Table B + register "fast_ppt_limit_mW_B" = "20000" + register "slow_ppt_limit_mW_B" = "13000" + register "slow_ppt_time_constant_s_B" = "5" + register "sustained_power_limit_mW_B" = "10000" + + register "stt_min_limit_B" = "5000" + register "stt_m1_B" = "0x11F" + register "stt_m2_B" = "0x3AE" + register "stt_c_apu_B" = "0xE19A" + register "stt_skin_temp_apu_B" = "0x3400" + + # Set Dynamic DPTC thermal profile confiuration. Table C + register "fast_ppt_limit_mW_C" = "30000" + register "slow_ppt_limit_mW_C" = "22000" + register "slow_ppt_time_constant_s_C" = "10" + register "sustained_power_limit_mW_C" = "15000" + + register "stt_min_limit_C" = "10000" + register "stt_m1_C" = "0x1A4" + register "stt_m2_C" = "0x2E1" + register "stt_c_apu_C" = "0xDACD" + register "stt_skin_temp_apu_C" = "0x3600" + + # Set Dynamic DPTC thermal profile confiuration. Table D + register "fast_ppt_limit_mW_D" = "25000" + register "slow_ppt_limit_mW_D" = "15000" + register "slow_ppt_time_constant_s_D" = "8" + register "sustained_power_limit_mW_D" = "10000" + + register "stt_min_limit_D" = "8000" + register "stt_m1_D" = "0x1C3" + register "stt_m2_D" = "0x2BB" + register "stt_c_apu_D" = "0xDE00" + register "stt_skin_temp_apu_D" = "0x3800" + + # Set Dynamic DPTC thermal profile confiuration. Table E + register "fast_ppt_limit_mW_E" = "22000" + register "slow_ppt_limit_mW_E" = "15000" + register "slow_ppt_time_constant_s_E" = "4" + register "sustained_power_limit_mW_E" = "12000" + + register "stt_min_limit_E" = "7000" + register "stt_m1_E" = "0x114" + register "stt_m2_E" = "0x371" + register "stt_c_apu_E" = "0xE333" + register "stt_skin_temp_apu_E" = "0x3000" + + + # Set Dynamic DPTC thermal profile confiuration. Table F + register "fast_ppt_limit_mW_F" = "18000" + register "slow_ppt_limit_mW_F" = "12000" + register "slow_ppt_time_constant_s_F" = "2" + register "sustained_power_limit_mW_F" = "9000" + + register "stt_min_limit_F" = "5000" + register "stt_m1_F" = "0x15C" + register "stt_m2_F" = "0x33D" + register "stt_c_apu_F" = "0xE866" + register "stt_skin_temp_apu_F" = "0x3200" + + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_hcnt = 107, + .scl_lcnt = 230, + .sda_hold = 100 + } + }" + + device domain 0 on + + register "dxio_tx_vboost_enable" = "1" + + device ref gpp_bridge_1 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # eMMC + device ref gpp_bridge_2 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe + + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref xhci_1 on # XHCI1 controller + chip drivers/usb/acpi + device ref xhci_1_root_hub on # XHCI1 root hub + chip drivers/usb/acpi + device ref usb3_port3 on # USB 3.1 port3 + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + device usb 3.2 on end + end + end # USB 3.1 port3 + end + chip drivers/usb/acpi + device ref usb2_port3 on # USB 2 port3 + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + device usb 2.2 on end + end + end # USB 2 port3 + end + end # XHCI1 root hub + end + end # XHCI1 controller + end # Internal GPP Bridge 0 to Bus A + end # domain + + device ref i2c_0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" + register "wake" = "GEVENT_20" + register "detect" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GXTP7863"" + register "generic.desc" = ""Goodix Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)" + register "generic.wake" = "GEVENT_20" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end # I2C0 + device ref i2c_1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN900C"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)" + register "generic.detect" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" + register "generic.enable_delay_ms" = "10" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" + register "generic.reset_off_delay_ms" = "1" + register "generic.reset_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)" + register "generic.stop_delay_ms" = "180" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""MLFS0000"" + register "desc" = ""Melfas Touchscreen"" + register "detect" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_29)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "2" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)" + register "stop_off_delay_ms" = "2" + register "has_power_resource" = "1" + device i2c 34 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_3)" + register "key.dev_name" = ""EJCT"" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + register "key.debounce_interval" = "100" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + device generic 0 on end + end + end # I2C1 + device ref i2c_2 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1019"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1019"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "2" + register "probed" = "1" + device i2c 2a on end + end + end # I2C2 + + device ref uart_1 on + chip drivers/uart/acpi + register "name" = ""CRFP"" + register "desc" = ""Fingerprint Reader"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cros-ec-uart"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_24)" + register "wake" = "GEVENT_15" + register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_4)" + register "enable_delay_ms" = "3" + device generic 0 alias fpmcu on end + end + end # UART1 + +end # chip soc/amd/mendocino -- cgit v1.2.3