From ac490b8a6bb31bf39fe8087ac3ba6a9b814beb87 Mon Sep 17 00:00:00 2001 From: "jinkun.hong" Date: Sun, 22 Jun 2014 20:40:39 -0700 Subject: coreboot: rk3288: Add a stub implementation of the rk3288 SOC Most things still needs to be filled in, but this will allow us to build boards which use this SOC. BUG=chrome-os-partner:29778 TEST=emerge-veyron coreboot Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc Original-Signed-off-by: jinkun.hong Original-Reviewed-on: https://chromium-review.googlesource.com/205069 Original-Reviewed-by: Julius Werner Original-Reviewed-by: David Hendricks Original-Commit-Queue: David Hendricks Original-Tested-by: David Hendricks (cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb) Signed-off-by: Marc Jones Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239 Reviewed-on: http://review.coreboot.org/8653 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/Kconfig | 3 ++ src/mainboard/google/veyron/Kconfig | 59 +++++++++++++++++++++++++++++++ src/mainboard/google/veyron/Makefile.inc | 23 ++++++++++++ src/mainboard/google/veyron/chromeos.c | 46 ++++++++++++++++++++++++ src/mainboard/google/veyron/devicetree.cb | 49 +++++++++++++++++++++++++ src/mainboard/google/veyron/mainboard.c | 51 ++++++++++++++++++++++++++ src/mainboard/google/veyron/romstage.c | 59 +++++++++++++++++++++++++++++++ 7 files changed, 290 insertions(+) create mode 100644 src/mainboard/google/veyron/Kconfig create mode 100644 src/mainboard/google/veyron/Makefile.inc create mode 100644 src/mainboard/google/veyron/chromeos.c create mode 100644 src/mainboard/google/veyron/devicetree.cb create mode 100644 src/mainboard/google/veyron/mainboard.c create mode 100644 src/mainboard/google/veyron/romstage.c (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index 210bf46c05..fb1ead6c16 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -59,6 +59,8 @@ config BOARD_GOOGLE_STORM bool "Storm" config BOARD_GOOGLE_STOUT bool "Stout" +config BOARD_GOOGLE_VEYRON + bool "Veyron" endchoice @@ -81,6 +83,7 @@ source "src/mainboard/google/samus/Kconfig" source "src/mainboard/google/slippy/Kconfig" source "src/mainboard/google/storm/Kconfig" source "src/mainboard/google/stout/Kconfig" +source "src/mainboard/google/veyron/Kconfig" config MAINBOARD_VENDOR string "Mainboard Vendor" diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig new file mode 100644 index 0000000000..bbbc617d92 --- /dev/null +++ b/src/mainboard/google/veyron/Kconfig @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_VEYRON + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_SPI + select SOC_ROCKCHIP_RK3288 + select MAINBOARD_DO_NATIVE_VGA_INIT + select BOARD_ROMSIZE_KB_4096 + +config MAINBOARD_DIR + string + default google/veyron + +config MAINBOARD_PART_NUMBER + string + default "Veyron" + +config MAINBOARD_VENDOR + string + default "Google" + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 1 + +config DRAM_DMA_START + hex + default 0x10000000 + +config DRAM_DMA_SIZE + hex + default 0x00200000 + +config DRAM_SIZE_MB + int + default 2048 + +endif # BOARD_GOOGLE_VEYRON diff --git a/src/mainboard/google/veyron/Makefile.inc b/src/mainboard/google/veyron/Makefile.inc new file mode 100644 index 0000000000..50a6ba039b --- /dev/null +++ b/src/mainboard/google/veyron/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += romstage.c +ramstage-y += mainboard.c +ramstage-y += chromeos.c + diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c new file mode 100644 index 0000000000..f396b4b016 --- /dev/null +++ b/src/mainboard/google/veyron/chromeos.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include + + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + return 0; +} diff --git a/src/mainboard/google/veyron/devicetree.cb b/src/mainboard/google/veyron/devicetree.cb new file mode 100644 index 0000000000..0acbae9e18 --- /dev/null +++ b/src/mainboard/google/veyron/devicetree.cb @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# TODO fill with Versatile Express board data in QEMU. +chip soc/rockchip/rk3288 + device cpu_cluster 0 on end + #SCREEN_RGB + register "screen_type" = "2" + #LVDS_8BIT_2 + register "lvds_format" = "1" + #OUT_D888_P666 + register "out_face" = "33" + register "clock_frequency" = "71000000" + register "hactive" = "1280" + register "vactive" = "800" + register "hback_porch" = "100" + register "hfront_porch" = "18" + register "vback_porch" = "8" + register "vfront_porch" = "6" + register "hsync_len" = "10" + register "vsync_len" = "2" + register "hsync_active" = "0" + register "vsync_active" = "0" + register "de_active" = "0" + register "pixelclk_active" = "0" + register "swap_rb" = "0" + register "swap_rg" = "0" + register "swap_gb" = "0" + #LCD_EN_GPIO:GPIO7_A3 + register "lcd_en_gpio" = "0xff7e0004" + #LCD_CS_GPIO:GPIO7_A4 + register "lcd_cs_gpio" = "0xff7e0005" +end diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c new file mode 100644 index 0000000000..607b1d5bbe --- /dev/null +++ b/src/mainboard/google/veyron/mainboard.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +static void mainboard_init(device_t dev) +{ + +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = CONFIG_DRAM_DMA_START; + dma->range_size = CONFIG_DRAM_DMA_SIZE; +} diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c new file mode 100644 index 0000000000..b9daefe6b9 --- /dev/null +++ b/src/mainboard/google/veyron/romstage.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void main(void) +{ + void *entry; + + console_init(); + + /* used for MMU and CBMEM setup, in MB */ + u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); + u32 dram_size = CONFIG_DRAM_SIZE_MB; + u32 dram_end = dram_start + dram_size; + mmu_init(); + /* Device memory below DRAM is uncached. */ + mmu_config_range(0, dram_start, DCACHE_OFF); + /* DRAM is cached. */ + mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); + /* A window for DMA is uncached. */ + mmu_config_range(CONFIG_DRAM_DMA_START >> 20, + CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); + /* The space above DRAM is uncached. */ + if (dram_end < 4096) + mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); + mmu_disable_range(0, 1); + dcache_mmu_enable(); + + cbmem_initialize_empty(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + stage_exit(entry); +} -- cgit v1.2.3