From aaff4017d011041c99777a452f395fbd35546c35 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 27 Jun 2020 15:24:09 -0700 Subject: mb/google/kahlee: Do not enable SCI for H1_PCH_INT_ODL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit H1 is not a wake source and hence there is no need to configure SCI GEVENT for it. This change drops PAD_SCI() configuration for GPIO_9 i.e. H1_PCH_INT_ODL. BUG=b:159944426 Change-Id: Iec2285b76f9c5fa1b4b1be15128fea316fa04555 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/42874 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin --- src/mainboard/google/kahlee/variants/baseboard/gpio.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index abdcb0dde1..59d7631da2 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -18,9 +18,8 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = { /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */ PAD_SMI(GPIO_6, PULL_UP, LEVEL_LOW), - /* GPIO_9 - H1_PCH_INT_ODL, SCI */ + /* GPIO_9 - H1_PCH_INT_ODL */ PAD_INT(GPIO_9, PULL_UP, EDGE_LOW, STATUS), - PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW), /* GPIO_15 - EC_IN_RW_OD */ PAD_GPI(GPIO_15, PULL_UP), @@ -28,7 +27,7 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = { /* GPIO_22 - EC_SCI_ODL, SCI */ PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), - /* GPIO_24 - EC_PCH_WAKE_L */ + /* GPIO_24 - EC_PCH_WAKE_L, SCI */ PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), /* GPIO_26 - APU_PCIE_RST_L */ -- cgit v1.2.3