From a2e7ee729ee955d168d887aa73fe0e77024ec2f3 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 25 Apr 2019 09:06:49 -0700 Subject: mb/google/sarien: Enable LTR for PCIe NVMe root port Enable LTR for NVMe so it can use ASPM L1.2. BUG=b:127593309 TEST=build and boot on sarien and check L1 substate with lspci before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ after: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ Change-Id: I9842beda6767f758556747f83cfcedbd00612698 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/32456 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao Reviewed-by: Roy Mingi Park --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 1 + src/mainboard/google/sarien/variants/sarien/devicetree.cb | 1 + 2 files changed, 2 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 57c4e65e70..cf64c4bb89 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -196,6 +196,7 @@ chip soc/intel/cannonlake # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[4]" = "12" register "PcieClkSrcClkReq[4]" = "4" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 27c0913c6f..96146baf1e 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -197,6 +197,7 @@ chip soc/intel/cannonlake # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" -- cgit v1.2.3