From 9244358536aaecff29453b1693fdf202091878ef Mon Sep 17 00:00:00 2001 From: Tim Van Patten Date: Tue, 23 Aug 2022 16:06:33 -0600 Subject: soc/amd: Refactor DPTC Tablet Mode Refactor AMD DPTC tablet mode in preparation for adding low/no battery DPTC settings. 1. Refactor and simplify acpigen_write_alib_dptc() into the following functions: - acpigen_write_alib_dptc_default() - acpigen_write_alib_dptc_tablet() 2. Add device tree register value dptc_tablet_mode_enable to control whether DPTC tablet mode is enabled for a variant. 3. Add dptc.asl to perform the necessary ACPI checking before modifying the DPTC settings. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build nipperkin TEST=Boot skyrim Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0 Signed-off-by: Tim Van Patten Reviewed-on: https://review.coreboot.org/c/coreboot/+/66994 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/zork/variants/morphius/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index 3cf812650d..48747c4dfa 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -30,7 +30,7 @@ chip soc/amd/picasso register "telemetry_vddcr_soc_offset" = "0" # Set STAPM confiuration for tablet mode - register "dptc_enable" = "true" + register "dptc_tablet_mode_enable" = "true" register "slow_ppt_limit_tablet_mode_mW" = "20000" register "fast_ppt_limit_tablet_mode_mW" = "24000" register "sustained_power_limit_tablet_mode_mW" = "12000" -- cgit v1.2.3