From 90a825a7bcb775827c5caa678794138e71df9930 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 7 Mar 2023 16:34:22 +0000 Subject: mb/google/rex: Enable SaGv This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be able to train memory (DIMM) at different frequencies. On all latest Intel based platforms SaGv is expected to be enabled to support dynamic switching of memory operating frequency. BUG=b:267879107 TEST=Able to verify SaGv is enabled with 3 work point (0, 1 and 2) and MRC retraining takes around ~20ms extra compared to SaGv being disabled. Signed-off-by: Subrata Banik Change-Id: Ic680bfeab4dd285c0d3916ba5e917cc12bae3284 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73534 Reviewed-by: Kapil Porwal Reviewed-by: Sridhar Siricilla Tested-by: build bot (Jenkins) --- src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 9a71e959c3..09d49d05a9 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -39,6 +39,8 @@ chip soc/intel/meteorlake # Enable CNVi BT register "cnvi_bt_core" = "true" + register "sagv" = "SAGV_ENABLED" + # Set on-board graphics as primary display register "skip_ext_gfx_scan" = "1" -- cgit v1.2.3