From 8a039031dd69e7c6d970eef1e8841aae5c888b0d Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 27 Jul 2022 17:58:02 +0000
Subject: mb/google/rex: Enable CNVi BT Core

This patch override `CnviBtCore` FSP UPD.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I90c9b360969aada0b0e031d62b48476fac5cee0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
---
 src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/mainboard/google')

diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index e669c128dd..3471c7e805 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -11,6 +11,9 @@ chip soc/intel/meteorlake
 	# EC memory map range is 0x900-0x9ff
 	register "gen3_dec" = "0x00fc0901"
 
+	# Enable CNVi BT
+	register "cnvi_bt_core" = "true"
+
 	register "serial_io_uart_mode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoPci,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
-- 
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