From 89e7b49a114f60f2fddf5f409dea0025785d4604 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Thu, 14 Jul 2016 09:52:00 -0700 Subject: soc/intel/apollolake: Consolidate ISH enabling Since the Integrated Sensor Hub can be disabled through devicetree.cb as a PCI device, there is no need for a separate register variable. Remove handling the register and update mainboards' devicetrees. Also keep ISH disabled on both Reef and Amenia. Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/15710 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/reef/devicetree.cb | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index 3425c432b3..34f0b03f52 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -6,11 +6,6 @@ chip soc/intel/apollolake register "pcie_rp4_clkreq_pin" = "0" # wifi/bt - # TODO(furquan): Remove this once global reset issue is fixed in later - # steppings. - # Integrated Sensor Hub - register "integrated_sensor_hub_enable" = "1" - # EMMC TX DATA Delay 1# # 0x0C[14:8] stands for 12*125 = 1500 pSec delay for HS400 # 0x11[6:0] stands for 17*125 = 2125 pSec delay for SDR104/HS200 @@ -61,7 +56,7 @@ chip soc/intel/apollolake device generic 0 on end end end - device pci 11.0 on end # - ISH + device pci 11.0 off end # - ISH device pci 12.0 off end # - SATA device pci 13.0 off end # - Root Port 2 - PCIe-A 0 device pci 13.1 off end # - Root Port 3 - PCIe-A 1 -- cgit v1.2.3