From 83ca56acdfc7a98945f673c7739764ef25b967f2 Mon Sep 17 00:00:00 2001 From: David Wu Date: Wed, 10 Jun 2020 20:16:07 +0800 Subject: mb/google/volteer/var/terrador: Update dq/dqs mappings Update dq/dqs mappings based on terrador schematics. BUG=b:156435028,b:151978872 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu Change-Id: I97697a3dd9b88eaffe6e2b1be7bd346979cbc956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42247 Tested-by: build bot (Jenkins) Reviewed-by: Kane Chen Reviewed-by: Furquan Shaikh --- .../google/volteer/variants/terrador/Makefile.inc | 2 + .../google/volteer/variants/terrador/memory.c | 60 ++++++++++++++++++++++ 2 files changed, 62 insertions(+) create mode 100644 src/mainboard/google/volteer/variants/terrador/memory.c (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/volteer/variants/terrador/Makefile.inc b/src/mainboard/google/volteer/variants/terrador/Makefile.inc index c9a128d72a..3a7557b548 100644 --- a/src/mainboard/google/volteer/variants/terrador/Makefile.inc +++ b/src/mainboard/google/volteer/variants/terrador/Makefile.inc @@ -4,4 +4,6 @@ SPD_SOURCES = bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/terrador/memory.c b/src/mainboard/google/volteer/variants/terrador/memory.c new file mode 100644 index 0000000000..773e88561d --- /dev/null +++ b/src/mainboard/google/volteer/variants/terrador/memory.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg terrador_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct lpddr4x_cfg *variant_memory_params(void) +{ + return &terrador_memcfg; +} -- cgit v1.2.3