From 7f844ab8b710e3244d1e681e800d99163cc9c65f Mon Sep 17 00:00:00 2001 From: Jes Klinke Date: Fri, 28 Aug 2020 13:44:21 -0700 Subject: mainboard/google/volteer: Disable S0i3.4 if cr50 firmware is too old For Volteer (and future Tiger Lake boards) we can enable mode S0i3.4 only if we know that the Cr50 is generating 100us interrupt pulses. We have to do so, because the SoC is not guaranteed to detect pulses shorter than 100us in S0i3.4 substate. A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code running in verstage, which will program a new Cr50 register, provided that Cr50 firmware is new enough to support the register. This CL adds code to detect the case when Cr50 is unable to generate longer pulses, and in that case explicitly disable the S0i3.4 substate as well as setting gpio_pm_override to all zeroes. This will increase power usage slightly, but guarantee that the GPIO block in the SoC does not switch to a slower sampling clock. In practice, this case will only be encountered in the factory, before the Cr50 chip is updated to a new RW image. (Prior to this change, the gpio_pm_override was hardcoded to zero for Volteer, but the S0i3.4 substate was not disabled. According to my conversations with Intel engineers, that was not enough to guarantee detection pulses shorter than 100us. But it is entirely possible that we have just been "lucky" that the SoC has not gone into low power mode during the boot process, where most of the cr50 communication happens.) TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x BUG=b:154333137 Change-Id: Idef1fffd410a345678da4b3c8aea46ac74a01470 Signed-off-by: Jes Bodi Klinke Reviewed-on: https://review.coreboot.org/c/coreboot/+/44359 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/volteer/mainboard.c | 20 ++++++++++++++++++++ .../google/volteer/variants/baseboard/devicetree.cb | 8 -------- 2 files changed, 20 insertions(+), 8 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index ead187e0d7..849869a2c8 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -4,9 +4,12 @@ #include #include #include +#include #include #include +#include #include +#include #include #include @@ -38,6 +41,23 @@ static void mainboard_enable(struct device *dev) dev->ops->get_smbios_strings = mainboard_smbios_strings; } +void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg) +{ + tlcl_lib_init(); + if (cr50_is_long_interrupt_pulse_enabled()) { + printk(BIOS_INFO, "Enabling S0i3.4\n"); + } else { + /* + * Disable S0i3.4, preventing the GPIO block from switching to + * slow clock. + */ + printk(BIOS_INFO, "Not enabling S0i3.4\n"); + cfg->LpmStateDisableMask |= LPM_S0i3_4; + cfg->gpio_override_pm = 1; + memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm)); + } +} + static void mainboard_chip_init(void *chip_info) { const struct pad_config *base_pads; diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 3e9e02ce53..1b8b0d6d03 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -187,14 +187,6 @@ chip soc/intel/tigerlake register "DdiPort3Ddc" = "0" register "DdiPort4Ddc" = "0" - # Disable PM to allow for shorter irq pulses - register "gpio_override_pm" = "1" - register "gpio_pm[0]" = "0" - register "gpio_pm[1]" = "0" - register "gpio_pm[2]" = "0" - register "gpio_pm[3]" = "0" - register "gpio_pm[4]" = "0" - # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" -- cgit v1.2.3