From 7eb2a9ad4fb8013c0e8385d21bbefd8e3b4141e8 Mon Sep 17 00:00:00 2001 From: Tyler Wang Date: Thu, 7 Nov 2024 16:37:26 +0800 Subject: mb/google/rex/var/kanix: Add USB A1 port support BUG=b:366291025 TEST=emerge-rex coreboot pass Change-Id: Ie76b20cab9e15a1944451697ebf243c0f0cc4740 Signed-off-by: Tyler Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/85105 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Kapil Porwal --- src/mainboard/google/rex/variants/kanix/gpio.c | 4 ++-- src/mainboard/google/rex/variants/kanix/overridetree.cb | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/rex/variants/kanix/gpio.c b/src/mainboard/google/rex/variants/kanix/gpio.c index b512c196da..202dae65e6 100644 --- a/src/mainboard/google/rex/variants/kanix/gpio.c +++ b/src/mainboard/google/rex/variants/kanix/gpio.c @@ -205,8 +205,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E07, NONE), /* GPP_E08 : NC net. */ PAD_NC(GPP_E08, NONE), - /* GPP_E09 : SOC_PEN_DETECT */ - PAD_CFG_GPI_SCI_LOCK(GPP_E09, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG), + /* GPP_E09 : [] ==> USB_OC0# */ + PAD_CFG_NF_LOCK(GPP_E09, NONE, NF1, LOCK_CONFIG), /* GPP_E10 : [] ==> SOC_FPMCU_INT_L */ PAD_CFG_GPI_IRQ_WAKE(GPP_E10, NONE, PWROK, LEVEL, INVERT), /* GPP_E11 : [] ==> MEM_STRAP_0 */ diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb index 6c8a1580ba..012657c1dd 100644 --- a/src/mainboard/google/rex/variants/kanix/overridetree.cb +++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb @@ -2,10 +2,12 @@ chip soc/intel/meteorlake register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port A1 register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0 register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1 @@ -288,6 +290,13 @@ chip soc/intel/meteorlake register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port2 on end end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port8 on end + end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" @@ -308,6 +317,13 @@ chip soc/intel/meteorlake register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port1 on end end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end end end end -- cgit v1.2.3