From 77d37d21dbb0a52cdf0af17bf20b8ff49ba69256 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 30 Oct 2015 17:55:05 -0700 Subject: google/chell: Fix USB port assignment The PCH pin names in the schematic were incorrectly labeled. BUG=chrome-os-partner:46289 BRANCH=none TEST=build and boot on chell Change-Id: I6153137b7c04d22db5b3f00f5eaf3f400f4c344c Signed-off-by: Patrick Georgi Original-Commit-Id: 6f362900b0635dc392c63b25a88a7723f22b467a Original-Change-Id: If6f8744f020a35a76647366b247723b03c02991a Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/310061 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/12324 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/chell/devicetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index dfa588a86f..05e37bfbfe 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -54,11 +54,11 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[4]" = "2" register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_MID" # Type-A Port - register "usb2_ports[2]" = "USB2_PORT_FLEX" # Camera + register "usb2_ports[2]" = "USB2_PORT_TYPE_C" # Type-C Port 2 register "usb2_ports[3]" = "USB2_PORT_MID" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID" # SD - register "usb2_ports[5]" = "USB2_PORT_TYPE_C" # Type-C Port 2 + register "usb2_ports[5]" = "USB2_PORT_MID" # Type-A Port + register "usb2_ports[7]" = "USB2_PORT_FLEX" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID" # SD register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2 -- cgit v1.2.3