From 75f701799a789b3d80eb90a441539be55fd0f5b2 Mon Sep 17 00:00:00 2001 From: Jimmy Zhang Date: Mon, 21 Apr 2014 15:58:45 -0700 Subject: nyan*: Add fast link training functions Some panels (including those on Big DVT) cannot work fine without link training before sending the video signals, especially multi-lane Full HD panels. We need to use the fast link training functions from kernel to support them. BRANCH=Nyan BUG=chrome-os-partner:28128, chrome-os-partner:28129 TEST=tested on nyan, nyan_big dvt. Vince verified on Full HD panels. Signed-off-by: Jimmy Zhang Original-Change-Id: Ifde8daf0ebdc6fb407610d3563f3311b2a72dbc4 Original-Reviewed-on: https://chromium-review.googlesource.com/196162 Original-Reviewed-by: Hung-Te Lin Original-Commit-Queue: Hung-Te Lin Original-Tested-by: Hung-Te Lin (cherry picked from commit 992132ff3431fc7abba10cc8e910e36d4f3a3f7a) Signed-off-by: Marc Jones Change-Id: I5ed091ae7a872fd674ab21f9f80267052fcd24b1 Reviewed-on: http://review.coreboot.org/7864 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/nyan/devicetree.cb | 4 ++-- src/mainboard/google/nyan_big/devicetree.cb | 4 ++-- src/mainboard/google/nyan_blaze/devicetree.cb | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb index e7ae54d52b..8919941360 100644 --- a/src/mainboard/google/nyan/devicetree.cb +++ b/src/mainboard/google/nyan/devicetree.cb @@ -88,7 +88,7 @@ chip soc/nvidia/tegra124 register "link_bw" = "10" # "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h - register "drive_current" = "0x13131313" - register "preemphasis" = "0x00000000" + register "drive_current" = "0x40404040" + register "preemphasis" = "0x0f0f0f0f" register "postcursor" = "0" end diff --git a/src/mainboard/google/nyan_big/devicetree.cb b/src/mainboard/google/nyan_big/devicetree.cb index e7ae54d52b..8919941360 100644 --- a/src/mainboard/google/nyan_big/devicetree.cb +++ b/src/mainboard/google/nyan_big/devicetree.cb @@ -88,7 +88,7 @@ chip soc/nvidia/tegra124 register "link_bw" = "10" # "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h - register "drive_current" = "0x13131313" - register "preemphasis" = "0x00000000" + register "drive_current" = "0x40404040" + register "preemphasis" = "0x0f0f0f0f" register "postcursor" = "0" end diff --git a/src/mainboard/google/nyan_blaze/devicetree.cb b/src/mainboard/google/nyan_blaze/devicetree.cb index e7ae54d52b..8919941360 100644 --- a/src/mainboard/google/nyan_blaze/devicetree.cb +++ b/src/mainboard/google/nyan_blaze/devicetree.cb @@ -88,7 +88,7 @@ chip soc/nvidia/tegra124 register "link_bw" = "10" # "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h - register "drive_current" = "0x13131313" - register "preemphasis" = "0x00000000" + register "drive_current" = "0x40404040" + register "preemphasis" = "0x0f0f0f0f" register "postcursor" = "0" end -- cgit v1.2.3