From 70ca84d6e7a2a591ca32c14ca927d9c636ec75d0 Mon Sep 17 00:00:00 2001 From: caveh jalali Date: Tue, 11 Jun 2019 04:23:23 +0000 Subject: Revert "mb/google/poppy/variants/atlas: enable NVMe" This reverts commit 41979d862a972375d6800afdf2b8b52d408fd220. Reason for revert: NVMe is no longer supported. BUG=b:134752066 Change-Id: I95f2e5f5efe2417700d458f0efd3c793fd8ce8c3 Signed-off-by: Caveh Jalali Reviewed-on: https://review.coreboot.org/c/coreboot/+/33307 Reviewed-by: Furquan Shaikh Reviewed-by: Bob Moragues Tested-by: build bot (Jenkins) --- src/mainboard/google/poppy/variants/atlas/devicetree.cb | 16 +--------------- src/mainboard/google/poppy/variants/atlas/gpio.c | 4 ++-- 2 files changed, 3 insertions(+), 17 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 1ea28a0e5f..7fcb3b8b3e 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -155,20 +155,6 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" - # PCIe Root port 5 (NVMe) - # PcieRpEnable: Enable root port - # PcieRpClkReqSupport: Enable CLKREQ# - # PcieRpClkReqNumber: Uses SRCCLKREQ4# - # PcieRpClkSrcNumber: Uses CLKOUT_PCIE_4 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting - # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism - register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqNumber[4]" = "4" - register "PcieRpClkSrcNumber[4]" = "4" - register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" - # USB 2.0 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty @@ -374,7 +360,7 @@ chip soc/intel/skylake device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 (NVMe) + device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index 372c66a5a0..5cc1a4fc5d 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -78,8 +78,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NC(GPP_B7), /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), - /* B9 : SRCCLKREQ4# ==> NVME_PCIE_CLKREQ_L */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B9 : SRCCLKREQ4# ==> NC */ + PAD_CFG_NC(GPP_B9), /* B10 : SRCCLKREQ5# ==> NC */ PAD_CFG_NC(GPP_B10), /* B11 : EXT_PWR_GATE# ==> NC */ -- cgit v1.2.3