From 6d6298dddc4147e7a1df6c51cb97b3d94e9c4584 Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Sat, 11 Jan 2014 07:46:50 +0100 Subject: ibexpeak / bd82x6x: Make SATA mode user-visible option. Ability to choose compatibility mode is interesting for testing payloads and OS for compatibility with older systems. As per comments "ide_legacy_combined # TODO: Does nothing since generations, remove from sb code?" The "combined" mode was removed. It wasn't used by any mobo and the code for it is almost identical to IDE one other than few bits relating to interrupt handling and ISA mode. Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/4658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/google/butterfly/cmos.layout | 5 ++++- src/mainboard/google/butterfly/devicetree.cb | 2 -- src/mainboard/google/link/cmos.layout | 5 ++++- src/mainboard/google/link/devicetree.cb | 2 -- src/mainboard/google/parrot/cmos.layout | 5 ++++- src/mainboard/google/parrot/devicetree.cb | 2 -- src/mainboard/google/stout/cmos.layout | 5 ++++- src/mainboard/google/stout/devicetree.cb | 2 -- 8 files changed, 16 insertions(+), 12 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index 05de624705..ee5ee256c1 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -132,6 +133,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index e7a50c0c57..9a7a1d571e 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -56,8 +56,6 @@ chip northbridge/intel/sandybridge #register "gpi1_routing" = "1" #SMI from EC register "gpi13_routing" = "2" #SCI from EC - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" # Enable SATA ports 0 & 1 register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index afdd3c66ca..b7320b5b99 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 15f420d056..8f0ed3c7e8 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge register "gpi7_routing" = "2" register "gpi8_routing" = "1" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sata_port0_gen3_tx" = "0x00880a7f" diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index afdd3c66ca..b7320b5b99 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index cd65fbf9a4..59586cc784 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -61,8 +61,6 @@ chip northbridge/intel/sandybridge register "gpi8_routing" = "1" register "gpi15_routing" = "1" #lid switch gpe - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" # EC range is 0xFD60 (EC_IO) and 0x68/0x6C diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index afdd3c66ca..b7320b5b99 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 6e02020890..653d3fe424 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "1" register "gpi6_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s register "sata_interface_speed_support" = "0x2" -- cgit v1.2.3