From 5d8f4badda7b8cb0a26312454efef3beabc2f8f0 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 14 Oct 2021 10:02:51 -0700 Subject: mb/google/brya: Set same size for CSE_RW, ME_RW_A and ME_RW_B CSE RW firmware from ME_RW_A/ME_RW_B is copied over to CSE_RW region in case of firmware update. Ensure that the size of the regions match so that we do not have situations where ME_RW_A/B firmware grows bigger than what CSE_RW can hold. BUG=b:189177538 Change-Id: I374db5d490292eeb98f67dc684c2106d42779dac Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58213 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/chromeos.fmd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd index 4b918750b9..72c6429672 100644 --- a/src/mainboard/google/brya/chromeos.fmd +++ b/src/mainboard/google/brya/chromeos.fmd @@ -14,7 +14,7 @@ FLASH 32M { VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3M + ME_RW_A(CBFS) 3008K } RW_LEGACY(CBFS) 2M RW_MISC 1M { @@ -43,7 +43,7 @@ FLASH 32M { VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3M + ME_RW_B(CBFS) 3008K } # Make WP_RO region align with SPI vendor # memory protected range specification. -- cgit v1.2.3