From 5d3d69ca950c728878d3fb0a26bc3be0b91bf406 Mon Sep 17 00:00:00 2001 From: Jagadish Krishnamoorthy Date: Thu, 4 Aug 2016 10:17:22 -0700 Subject: google/reef: Configure SDIO D1 to enable SCS Power Gating SDIO D1 pin needs to be configured as Native mode to enable SCS Power Gating. BUG=chrome-os-partner:54251 TEST=Verify SCS Power Gating Change-Id: Ic33b26443203217678e11d195eb965a7e628ad82 Signed-off-by: Jagadish Krishnamoorthy Reviewed-on: https://review.coreboot.org/16062 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/reef/gpio.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 4230c62ef7..be7f50193d 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -53,7 +53,8 @@ static const struct pad_config gpio_table[] = { /* SDIO -- unused. */ PAD_CFG_GPI(GPIO_166, UP_20K, DEEP), /* SDIO_CLK */ PAD_CFG_GPI(GPIO_167, UP_20K, DEEP), /* SDIO_D0 */ - PAD_CFG_GPI(GPIO_168, UP_20K, DEEP), /* SDIO_D1 */ + /* Configure SDIO to enable power gating */ + PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */ PAD_CFG_GPI(GPIO_169, UP_20K, DEEP), /* SDIO_D2 */ PAD_CFG_GPI(GPIO_170, UP_20K, DEEP), /* SDIO_D3 */ PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */ -- cgit v1.2.3