From 44d0ddcc817708403068893a5b4f72454deea355 Mon Sep 17 00:00:00 2001 From: Chiranjeevi Rapolu Date: Wed, 3 Aug 2016 14:09:33 -0700 Subject: google/reef: Correct SD card pins config SD CLK and CLK_FB needs to be pulled down by 20K. SD CD_N is active LOW, needs to be pulled up by 20K SD WP pin is not connected for uSD cards, enable writes by default by pulling low by 20K. BUG=chrome-os-partner:54866 BRANCH=None TEST=Test with uSD cards. Change-Id: Ia4bbd966ffb21e276dfc31a74f4ea54718900d66 Signed-off-by: Chiranjeevi Rapolu Reviewed-on: https://review.coreboot.org/16057 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/reef/gpio.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 969b39296a..5eb1d1dc29 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -59,15 +59,19 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */ /* SDCARD */ - PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1), /* SDCARD_CLK */ + /* Pull down clock by 20K */ + PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ - PAD_CFG_NF(GPIO_177, NATIVE, DEEP, NF1), /* SDCARD_CD_N */ + /* Card detect is active LOW. Pull up by 20K */ + PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */ PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ - PAD_CFG_NF(GPIO_179, NATIVE, DEEP, NF1), /* SDCARD_CLK_FB */ - PAD_CFG_NF(GPIO_186, NATIVE, DEEP, NF1), /* SDCARD_LVL_WP */ + /* CLK feedback, internal signal, needs 20K pull down */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */ + /* No h/w write proect for uSD cards, pull down by 20K */ + PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1), /* SDCARD_LVL_WP */ /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */ PAD_CFG_GPO(GPIO_183, 0, DEEP), /* SDIO_PWR_DOWN_N */ -- cgit v1.2.3