From 43b1066c0dd67a3d793298096b661cb6e03f65c4 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 4 Aug 2015 11:03:00 -0500 Subject: glados: enable SMBus device In order to run with the debug FSP the SMBus device needs to be enabled. Additionally, the TCO block lives within the SMBus device so if TCO is to be employed then the SMBus device needs to be enabled as a prerequisite. BUG=chrome-os-partner:42407 BRANCH=None TEST=Buit and booted into kernel. Original-Change-Id: I269650fa5222b4741ef495188dff1f4b8176fe89 Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/290364 Original-Reviewed-by: Bernie Thompson Original-Reviewed-by: Robbie Zhang Change-Id: Ia1f72ea7bd70728de83cdff07df9810a326266c2 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11181 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/google/glados/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index b48556f1d5..2e1cae75a8 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -44,7 +44,7 @@ chip soc/intel/skylake register "IshEnable" = "0" register "XdciEnable" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "0" + register "SmbusEnable" = "1" register "Cio2Enable" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -102,7 +102,7 @@ chip soc/intel/skylake end # LPC Interface device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel High Definition Audio - device pci 1f.4 off end # SMBus Controller + device pci 1f.4 on end # SMBus Controller device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE Controller end -- cgit v1.2.3