From 42b1b8069c35a4e86772b600ea0264503bf20470 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Mon, 26 Aug 2013 15:12:12 -0700 Subject: Exynos5420: ddr3: fine tuning the DDR3 timing values Fine tuning DDR timings value for better stability * Changed Data Driver Strength from 34 ohms to 30 ohms, expected to enhance signal integrity. * Changed DQ signal from 0xf to 0x1f000f, to keep default value safe. * Changed mrs[2] and added new mrs direct command for setting WL/RL without resetting DLL. * Added explicit reset value write in phy_con0 instead of just setting a bit, to ensure that reset happens. * Added DREX automatic control for ctrl_pd in none read memory state. This is ported from: https://gerrit.chromium.org/gerrit/61405 Signed-off-by: David Hendricks Change-Id: I59e96e6dede7b49c6572548aca664d82ad110bb1 Reviewed-on: https://chromium-review.googlesource.com/66995 Reviewed-by: ron minnich Commit-Queue: David Hendricks Tested-by: David Hendricks (cherry picked from commit ec34b711c6d270672c56d45c370ca14c0aa27ca3) Signed-off-by: Isaac Christensen Reviewed-on: http://review.coreboot.org/6611 Reviewed-by: David Hendricks Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel --- src/mainboard/google/pit/memory.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/pit/memory.c b/src/mainboard/google/pit/memory.c index 74f3e6eb9c..ddd7aa0ff1 100644 --- a/src/mainboard/google/pit/memory.c +++ b/src/mainboard/google/pit/memory.c @@ -32,7 +32,8 @@ const struct mem_timings mem_timings = { .mem_type = DDR_MODE_DDR3, .frequency_mhz = 800, .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010002, 0x00000d70 + 0x00020018, 0x00030000, 0x00010046, 0x00000d70, + 0x00000c70 }, .timing_ref = 0x000000bb, .timing_row = 0x6836650f, @@ -65,7 +66,7 @@ const struct mem_timings mem_timings = { .rd_fetch = 0x3, - .zq_mode_dds = 0x6, + .zq_mode_dds = 0x7, .zq_mode_term = 0x1, .zq_mode_noterm = 1, -- cgit v1.2.3