From 322aa801d2a95fd5cb2d7f2fc7b871c91ef180a9 Mon Sep 17 00:00:00 2001 From: Tyler Wang Date: Tue, 24 May 2022 18:37:24 +0800 Subject: mb/google/nissa/craask: Configure the external V1p05/Vnn/VnnSx This patch configures external V1p05/Vnn/VnnSx rails for Craask to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:233717182 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang Change-Id: I95d24c0836f3ee02006868341ccc72d762c155d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64632 Tested-by: build bot (Jenkins) Reviewed-by: Kangheui Won Reviewed-by: Reka Norman --- src/mainboard/google/brya/variants/craask/overridetree.cb | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index ac9173226a..55fc1e4056 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -31,6 +31,21 @@ chip soc/intel/alderlake register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + device domain 0 on device ref ipu on chip drivers/intel/mipi_camera -- cgit v1.2.3