From 309ccf74dd7c25874572c6a62ffc7042dcdadc66 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Sat, 9 May 2020 16:37:30 +0530 Subject: cannonlake: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Cannonlake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on drallion system Change-Id: Iac6e6f81343fcd769619e9d7ac339430966834f6 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41235 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 8 +++++--- src/mainboard/google/hatch/variants/akemi/overridetree.cb | 6 ++++-- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 6 ++++-- src/mainboard/google/hatch/variants/dratini/overridetree.cb | 6 ++++-- src/mainboard/google/hatch/variants/duffy/mainboard.c | 9 ++++++--- src/mainboard/google/hatch/variants/helios/overridetree.cb | 6 ++++-- .../google/hatch/variants/helios_diskswap/overridetree.cb | 6 ++++-- src/mainboard/google/hatch/variants/jinlon/overridetree.cb | 6 ++++-- src/mainboard/google/hatch/variants/kaisa/mainboard.c | 9 ++++++--- src/mainboard/google/hatch/variants/kindred/overridetree.cb | 6 ++++-- src/mainboard/google/hatch/variants/kohaku/overridetree.cb | 6 ++++-- src/mainboard/google/hatch/variants/mushu/overridetree.cb | 6 ++++-- src/mainboard/google/hatch/variants/nightfury/overridetree.cb | 6 ++++-- src/mainboard/google/hatch/variants/palkia/overridetree.cb | 6 ++++-- src/mainboard/google/hatch/variants/puff/mainboard.c | 7 +++++-- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 8 +++++--- src/mainboard/google/sarien/variants/sarien/devicetree.cb | 8 +++++--- 17 files changed, 76 insertions(+), 39 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 9bb09abd98..e9daf0d00d 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -42,11 +42,13 @@ chip soc/intel/cannonlake register "PchUsb2PhySusPgDisable" = "1" register "speed_shift_enable" = "1" - register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "tdp_pl1_override" = "25" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 51, + .psys_pmax = 140, + }" register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 27d11ccfb1..0e3972813a 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 9894e56324..2d3156ae6b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -37,8 +37,10 @@ chip soc/intel/cannonlake register "s0ix_enable" = "1" # Enable DPTF register "dptf_enable" = "1" - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "64" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 64, + }" register "Device4Enable" = "1" # Enable eDP device register "DdiPortEdp" = "1" diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 0bd3d8ee93..0bada7d916 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/duffy/mainboard.c b/src/mainboard/google/hatch/variants/duffy/mainboard.c index ef5df4ae4b..ecc0937fa8 100644 --- a/src/mainboard/google/hatch/variants/duffy/mainboard.c +++ b/src/mainboard/google/hatch/variants/duffy/mainboard.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #define GPIO_HDMI_HPD GPP_E13 @@ -86,7 +87,7 @@ static void wait_for_hpd(gpio_t gpio, long timeout) #define PSYS_IMAX 9600 #define BJ_VOLTS_MV 19000 -static void mainboard_set_power_limits(config_t *conf) +static void mainboard_set_power_limits(struct soc_power_limits_config *conf) { enum usb_chg_type type; u32 watts; @@ -123,7 +124,8 @@ static void mainboard_set_power_limits(config_t *conf) void variant_ramstage_init(void) { static const long display_timeout_ms = 3000; - config_t *conf = config_of_soc(); + struct soc_power_limits_config *soc_config; + config_t *confg = config_of_soc(); /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ gpio_input(GPIO_HDMI_HPD); @@ -136,5 +138,6 @@ void variant_ramstage_init(void) wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); } /* Psys_pmax needs to be setup before FSP-S */ - mainboard_set_power_limits(conf); + soc_config = &confg->power_limits_config; + mainboard_set_power_limits(soc_config); } diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 94639dcabe..0d73814249 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "64" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 64, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 8a3745d174..0422a57bd3 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "13" - register "tdp_pl2_override" = "64" + register "power_limits_config" = "{ + .tdp_pl1_override = 13, + .tdp_pl2_override = 64, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index 546267011d..a3bb782a36 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/kaisa/mainboard.c b/src/mainboard/google/hatch/variants/kaisa/mainboard.c index ef5df4ae4b..ecc0937fa8 100644 --- a/src/mainboard/google/hatch/variants/kaisa/mainboard.c +++ b/src/mainboard/google/hatch/variants/kaisa/mainboard.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #define GPIO_HDMI_HPD GPP_E13 @@ -86,7 +87,7 @@ static void wait_for_hpd(gpio_t gpio, long timeout) #define PSYS_IMAX 9600 #define BJ_VOLTS_MV 19000 -static void mainboard_set_power_limits(config_t *conf) +static void mainboard_set_power_limits(struct soc_power_limits_config *conf) { enum usb_chg_type type; u32 watts; @@ -123,7 +124,8 @@ static void mainboard_set_power_limits(config_t *conf) void variant_ramstage_init(void) { static const long display_timeout_ms = 3000; - config_t *conf = config_of_soc(); + struct soc_power_limits_config *soc_config; + config_t *confg = config_of_soc(); /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ gpio_input(GPIO_HDMI_HPD); @@ -136,5 +138,6 @@ void variant_ramstage_init(void) wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); } /* Psys_pmax needs to be setup before FSP-S */ - mainboard_set_power_limits(conf); + soc_config = &confg->power_limits_config; + mainboard_set_power_limits(soc_config); } diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index 8afae3968b..43fdfbf5fa 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 08bbb2a9b0..df18277408 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "8" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 8, + .tdp_pl2_override = 51, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 7bd1fac4e8..db86d68204 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -24,8 +24,10 @@ chip soc/intel/cannonlake register "FastPkgCRampDisableGt" = "1" register "FastPkgCRampDisableSa" = "1" - register "tdp_pl1_override" = "25" - register "tdp_pl2_override" = "44" + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 44, + }" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 2c759bc4bb..82f80a96f5 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index bce58011d3..31017bc01d 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "64" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 64, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/variants/puff/mainboard.c index ef5df4ae4b..b5bc699ca0 100644 --- a/src/mainboard/google/hatch/variants/puff/mainboard.c +++ b/src/mainboard/google/hatch/variants/puff/mainboard.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #define GPIO_HDMI_HPD GPP_E13 @@ -86,7 +87,7 @@ static void wait_for_hpd(gpio_t gpio, long timeout) #define PSYS_IMAX 9600 #define BJ_VOLTS_MV 19000 -static void mainboard_set_power_limits(config_t *conf) +static void mainboard_set_power_limits(struct soc_power_limits_config *conf) { enum usb_chg_type type; u32 watts; @@ -123,6 +124,7 @@ static void mainboard_set_power_limits(config_t *conf) void variant_ramstage_init(void) { static const long display_timeout_ms = 3000; + struct soc_power_limits_config *soc_config; config_t *conf = config_of_soc(); /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ @@ -136,5 +138,6 @@ void variant_ramstage_init(void) wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); } /* Psys_pmax needs to be setup before FSP-S */ - mainboard_set_power_limits(conf); + soc_config = &conf->power_limits_config; + mainboard_set_power_limits(soc_config); } diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index d1d9b038b2..a84e73a826 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -31,12 +31,14 @@ chip soc/intel/cannonlake register "PchUsb2PhySusPgDisable" = "1" register "speed_shift_enable" = "1" - register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "satapwroptimize" = "1" - register "tdp_pl1_override" = "25" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 51, + .psys_pmax = 140, + }" register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b2aa8d5e8d..09b4240993 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -42,9 +42,11 @@ chip soc/intel/cannonlake register "SlowSlewRateForGt" = "2" register "SlowSlewRateForSa" = "2" register "SlowSlewRateForFivr" = "2" - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" - register "psys_pmax" = "136" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + .psys_pmax = 136, + }" register "Device4Enable" = "1" # Enable eDP device register "DdiPortEdp" = "1" -- cgit v1.2.3