From 25fc070e35d45d8988a88ef1e22de60cd4041563 Mon Sep 17 00:00:00 2001 From: Patrick Huang Date: Tue, 10 Aug 2021 17:52:01 +0800 Subject: mb/google/guybrush/var/baseboard: Set Clk request for WLAN/SD/WWAN/SSD device Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (4/5/6) clock sources. In guybrush, clock source 0/1/2/3 are routed for WLAN/SD/WWAN/SSD device. BUG=b:186384256 BRANCH=none TEST=Verify the config setting can update to the GPPCLKCONTROL registers. Signed-off-by: Patrick Huang Change-Id: I240543e92cbc178cee034c37d7c26da0a6bbb7f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56895 Reviewed-by: Paul Menzel Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index c707c0fcc3..59efa43279 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -58,6 +58,15 @@ chip soc/amd/cezanne register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_REQ" + register "gpp_clk_config[4]" = "GPP_CLK_OFF" + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + register "pspp_policy" = "DXIO_PSPP_BALANCED" register "usb_phy_custom" = "1" -- cgit v1.2.3